Analog Devices Inc. LTC3861IUHE#PBF
- Part No.:
- LTC3861IUHE#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 36-WFQFN Exposed Pad
- Datasheet:
-
LTC3861IUHE#PBF.pdf
- Description:
- IC REG CTRLR BUCK 36QFN
- Quantity:
- Payment:

- Shipping:

Inventory:120
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Product details
Overview
LTC3861IUHE#PBF from Analog Devices (formerly Linear Technology) is a dual-channel, multiphase synchronous step-down voltage mode DC/DC controller designed for high-current power delivery to DSPs, FPGAs, and telecom systems. It supports 3V–24V input, 0.6V–(VCC–0.5V) output, 250kHz–2.25MHz programmable switching frequency, ±0.75% reference accuracy, and lossless DCR current sensing with accurate inter-phase current sharing.
For engineers reviewing the LTC3861IUHE#PBF datasheet, LTC3861IUHE#PBF pinout, LTC3861IUHE#PBF application, or LTC3861IUHE#PBF equivalent, key selection criteria include dual differential remote sense capability, 36-pin QFN thermal performance, multiphase scalability up to 12 phases, prebiased load startup safety, and VCC-supplied operation from 3V to 5.5V.
Technical Context
The LTC3861IUHE#PBF implements constant-frequency voltage-mode control with two independent error amplifiers (COMP1/COMP2), each driving its own PWM channel with dedicated FB/VSNSOUT/VSNSP/VSNSN signal paths. Its architecture integrates per-channel differential remote sensing, programmable soft-start via internal 2.5µA current source on TRACK/SS pins, and lossless inductor DCR current sensing using matched ISNS1P/ISNS1N and ISNS2P/ISNS2N inputs.
Phase synchronization is managed through CLKIN/CLKOUT daisy-chaining and PHSMD-programmable phase offsets (120°/180°), while current sharing across multiple ICs relies on IAVG bus coupling and master-slave COMP pin configuration. The controller operates with external gate drivers or DrMOS/power blocks and supports line feedforward compensation via VINSNS and CONFIG pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Range | 3V to 24V - supports wide-input industrial and telecom rails without external regulators. |
| VOUT Range | 0.6V to (VCC – 0.5V) - enables sub-1V core supplies for modern processors with no level-shifting circuitry. |
| Switching Frequency | 250kHz to 2.25MHz - adjustable via FREQ resistor or external CLKIN; enables optimization of size vs. efficiency trade-offs. |
| Reference Accuracy | ±0.75% at 0.6V - ensures tight output regulation across temperature and load for sensitive digital loads. |
| Operating Temp | –40°C to +125°C - qualified for industrial and extended-temperature embedded applications. |
| Package | 36-pin 5mm × 6mm QFN - exposed pad (Pin 37) must be soldered to SGND for θJA = 43°C/W thermal performance. |
| Current Sensing | Lossless DCR or precision resistor - eliminates sense resistor power loss while maintaining ±1.25mV offset over full temp range. |
Pinout & Package
Package: 36-lead plastic QFN (5mm × 6mm), exposed thermal pad (Pin 37 = SGND). Requires PCB soldering of exposed pad for rated thermal performance (θJA = 43°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FB1, FB2 (Pins 1, 10) | Error amplifier inverting input | Connects to VSNSOUTx for closed-loop regulation; tying to VCC disables respective channel's error amp and COMP output. |
| VSNSP1/VSNSN1, VSNSP2/VSNSN2 (Pins 3,4,7,8) | Differential remote sense inputs | VSNSP connects to feedback divider midpoint; VSNSN connects to load ground - cancels ground path IR drop for accurate remote sensing. |
| ISNS1P/ISNS1N, ISNS2P/ISNS2N (Pins 22,24,23,25) | Current sense amplifier inputs | Supports DCR sensing (across inductor) or discrete resistor placement; ±1.25mV max offset enables precise current sharing. |
| RUN1/RUN2 (Pins 19, 28) | Channel enable control | Logic-high (>2.25V) enables channel; <2V forces shutdown; internal 1.5µA pull-up allows simple resistor-based sequencing. |
| TRACK/SS1/SS2 (Pins 11, 35) | Soft-start and tracking input | Internal 2.5µA current source charges external capacitor for controlled ramp; also accepts external tracking voltage for coordinated multi-rail startup. |
| IAVG (Pin 32) | Average current monitor | Outputs voltage proportional to master-phase average current; must be tied together across paralleled ICs for current sharing; connect to SGND if channels operate independently. |
Key Features
| Feature | Design Value |
|---|---|
| Dual differential remote sensing | Two independent VSNSP/VSNSN/VSNSOUT paths eliminate ground loop errors for ±0.75% output regulation at point-of-load. |
| Multiphase scalability | Up to six LTC3861ICs can be daisy-chained via CLKOUT/CLKIN/PHSMD to achieve 1-, 2-, 3-, 4-, 6-, or 12-phase operation with synchronized timing. |
| Prebiased load startup | Inductor current reversal disabled during soft-start - prevents reverse current flow when powering already-biased outputs safely. |
| Programmable current limit | ILIM1/ILIM2 pins source 20µA; resistor-to-SGND sets overcurrent threshold with ±1.25mV sense offset compensated over –40°C to +125°C. |
| Line feedforward compensation | VINSNS + CONFIG pins enable instantaneous duty-cycle adjustment to VIN transients - reduces output overshoot/undershoot and decouples loop gain from input voltage. |
Applications
| Telecom Base Station Power | FPGA Core Supply |
|---|---|
Use Scenario: Distributed 12V-to-1.2V/60A supply for multi-core FPGA in 5G radio unit with strict transient response requirements. IC Role / Device Role / Timing Role: Dual-phase controller managing two parallel 30A phases with synchronized CLKOUT daisy-chain and IAVG-based current sharing. Use Value: Achieves <50µs load-step recovery (0→18A) and <100mV output deviation using 0.47µH inductors and 500kHz switching - enabled by high-bandwidth error amplifiers and feedforward compensation. | Use Scenario: High-efficiency, low-noise 1V/40A core rail for Xilinx Versal ACAP with prebiased auxiliary rails. IC Role / Device Role / Timing Role: Master-slave configured LTC3861IUHE#PBF pair with TRACK/SS1/SS2 enabling ratiometric startup of 1V core and 0.85V I/O rails. Use Value: Safely powers prebiased outputs without reverse current; maintains ±0.75% regulation across –40°C to +125°C ambient - critical for FPGA configuration stability. |
| Data Center ASIC Supply | Industrial Motor Control Logic |
Use Scenario: 48V intermediate bus converted to 0.8V/100A for AI accelerator ASIC with thermal constraints. IC Role / Device Role / Timing Role: Four LTC3861 controllers in 4-phase interleaved configuration, sharing IAVG bus and synchronized via CLKIN/CLKOUT. Use Value: Interleaving reduces input/output ripple by factor of √4; 2.25MHz max frequency allows compact 0.22µH inductors - shrinking solution size by >35% vs. single-phase design. | Use Scenario: Robust 3.3V/5A logic supply for servo drive microcontroller operating in noisy factory environments. IC Role / Device Role / Timing Role: Single-channel operation (RUN2 grounded) with VINSNS feedforward and differential remote sensing across long PCB traces. Use Value: Compensates for 200mV line drop under 5A load; maintains 3.3V ±15mV at connector despite 150mΩ trace resistance - enabled by VSNSP/VSNSN sensing topology. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel multiphase controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP2940AGQ-DC | Integrated MOSFET drivers; no external gate driver required; fixed 600kHz/1MHz options only; no IAVG bus for multi-IC current sharing. | Better suited for space-constrained designs where board area is premium and phase count ≤2; lacks scalable multiphase daisy-chain capability. | Select MP2940AGQ-DC when integrating gate drivers simplifies layout and system-level current sharing is not required beyond dual-phase. |
| LTC3883IUHF#PBF | Digital PMBus interface; integrated ADCs for telemetry; supports PID loop tuning via software; same 36-pin QFN package but different pinout and higher quiescent current. | Required where real-time monitoring, fault logging, or dynamic loop reconfiguration is needed - e.g., adaptive power management in test equipment. | Select LTC3883IUHF#PBF when digital control, telemetry, or field-upgradable firmware is mandatory; not drop-in compatible due to pinout and protocol differences. |
Compared with MP2940AGQ-DC and LTC3883IUHF#PBF, the LTC3861IUHE#PBF delivers superior analog control loop bandwidth, deterministic phase synchronization for >2-phase scaling, and hardware-based current sharing without software overhead - making it optimal for high-performance analog-regulated systems where predictability and transient response are critical.
Availability
LTC3861IUHE#PBF is available at Aetrix Electronics and suitable for telecom base station power, FPGA core supplies, and industrial motor control logic requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LTC3861IUHE#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its high-performance power management portfolio with rigorous automotive and industrial qualification standards.
The LTC3861IUHE#PBF belongs to Linear's PolyPhase® controller family, engineered specifically for high-current, low-voltage DC/DC conversion in distributed power architectures where phase interleaving, remote sensing, and robust transient response are essential.
FAQ
What is the maximum supported switching frequency for the LTC3861IUHE#PBF?
The LTC3861IUHE#PBF supports a maximum switching frequency of 2.25MHz when configured with an external clock on CLKIN. With the FREQ pin resistor method, the upper limit is 2.25MHz; internal presets are limited to 600kHz or 1MHz. This high-frequency capability enables use of smaller magnetics and capacitors in space-constrained applications while maintaining stable regulation.
How does the LTC3861IUHE#PBF handle prebiased output conditions during startup?
The LTC3861IUHE#PBF disables inductor current reversal during soft-start by default, preventing reverse current flow into a prebiased output. This behavior is inherent to its control architecture and requires no external components. The device monitors TRACK/SS pin voltage and suppresses bottom-FET turn-on until the output reaches regulation, ensuring safe startup into precharged loads like FPGA I/O banks or backup power rails.
Can the LTC3861IUHE#PBF operate with only one channel active?
Yes, the LTC3861IUHE#PBF supports single-channel operation. Tie RUN2 to SGND to disable Channel 2 while retaining full functionality on Channel 1 - including differential remote sensing (VSNSP1/VSNSN1), current limiting (ILIM1), and soft-start (TRACK/SS1). The unused COMP2, FB2, and related pins should be left unconnected or tied to VCC to disable their amplifiers, per datasheet guidance.
What is the purpose of the IAVG pin on the LTC3861IUHE#PBF?
IAVG (Pin 32) provides a voltage proportional to the instantaneous average current of the master phase in multiphase configurations. When multiple LTC3861IUHE#PBF ICs are paralleled, their IAVG pins must be tied together to enable hardware-based current sharing. If channels operate independently, IAVG must be connected to SGND to prevent erroneous current balancing signals from affecting regulation.
Does the LTC3861IUHE#PBF require external components for line feedforward compensation?
Yes - line feedforward compensation requires connection of VINSNS (Pin 34) to the input supply rail and proper configuration of CONFIG (Pin 33) to either VCC or SGND depending on VIN range and switching frequency. An optional RC low-pass filter may be added to VINSNS to reject noise, but the core feedforward function is implemented internally and activated automatically once VINSNS is properly biased.
LTC3861IUHE#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- PolyPhase®
- Package/Case:
- 36-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Output Type:
- PWM Signal
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Number of Outputs:
- 2
- Output Phases:
- 2
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Frequency - Switching:
- 250kHz ~ 3MHz
- Duty Cycle (Max):
- 91.5%
- Synchronous Rectifier:
- No
- Clock Sync:
- No
- Serial Interfaces:
- -
- Control Features:
- Current Limit, Enable, Frequency Control, Phase Control, Power Good, Soft Start, Tracking
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 36-QFN (5x6)
LTC3861IUHE#PBF FAQ
1.How can I place an order for LTC3861IUHE#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3861IUHE#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3861IUHE#PBF reliable?
The price and inventory of LTC3861IUHE#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3861IUHE#PBF is usually 5 days.
3.What payment methods are accepted for LTC3861IUHE#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3861IUHE#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3861IUHE#PBF?
LTC3861IUHE#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3861IUHE#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3861IUHE#PBF?
For technical support, including LTC3861IUHE#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3861IUHE#PBF requirements.
6.How does Aetrix verify that LTC3861IUHE#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3861IUHE#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3861IUHE#PBF meets industry standards.
7.What is the process for return or replacement of LTC3861IUHE#PBF?
All LTC3861IUHE#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3861IUHE#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3861IUHE#PBF part is unused and in its original packaging.
Return procedure for LTC3861IUHE#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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