Analog Devices Inc. LTC3862EGN-2#PBF
- Part No.:
- LTC3862EGN-2#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 24-SSOP (0.154", 3.90mm Width)
- Datasheet:
-
LTC3862EGN-2#PBF.pdf
- Description:
- IC REG CTRLR BOOST/SEPIC 24SSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC3862EGN-2#PBF from Analog Devices (formerly Linear Technology) is a two-phase, constant-frequency, peak current mode boost/SEPIC DC/DC controller driving external N-channel MOSFETs. It operates from 5.5V to 36V input, delivers up to 96% max duty cycle, supports 75kHz–500kHz programmable switching frequency, and features internal 10V/3.8V LDOs for gate drive and analog circuitry. It enables high-efficiency 80V output power supplies in telecom and industrial systems.
For engineers reviewing the LTC3862EGN-2#PBF datasheet, LTC3862EGN-2#PBF pinout, LTC3862EGN-2#PBF application, or LTC3862EGN-2#PBF equivalent, key selection criteria include its dual-phase current-mode architecture, INTVCC UVLO thresholds (4.4V rising / 3.9V falling), phase-programmable operation (2-/3-/4-/6-/12-phase via SYNC/CLKOUT/PHASEMODE), and 24-pin narrow SSOP package with exposed PGND pad.
Technical Context
The LTC3862EGN-2#PBF implements fixed-frequency, peak current mode control across two interleaved channels operating 180° out-of-phase, reducing input/output ripple and filter component stress. Its error amplifier compares FB voltage against a ±1% 1.223V reference and drives ITH to modulate peak inductor current per channel.
It integrates cascaded PMOS LDOs: a 10V INTVCC regulator (4.4V UVLO+, 3.9V UVLO−, 50mA RMS output) powers gate drivers, while a 3.8V LDO (bypassed with 1nF ceramic to SGND) supplies low-voltage analog/digital circuitry. Phase synchronization uses an internal PLL with SYNC input (50–650kHz) and CLKOUT output.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Topology | Two-phase boost/SEPIC controller - enables interleaved operation to halve input/output capacitor RMS current and reduce EMI. |
| Input Voltage Range | 5.5V to 36V - supports wide-range industrial and telecom inputs including 12V, 24V, and 32V bus rails. |
| Switching Frequency | 75kHz to 500kHz (resistor-programmable) - allows optimization of efficiency vs. size; also PLL-synchronizable from 50kHz to 650kHz. |
| Max Duty Cycle | 96% (DMAX = SGND), 84% (DMAX = float), 75% (DMAX = 3V8) - enables high step-up ratios (e.g., 12V→80V) without excessive on-time limitations. |
| Reference Voltage | 1.223V ±1% - precision feedback threshold enabling accurate output voltage regulation over temperature and line. |
| INTVCC UVLO Threshold | 4.4V (rising), 3.9V (falling) - ensures robust gate drive startup/shutdown for 6V-VGS rated MOSFETs. |
| Min On-Time | 210ns (BLANK = SGND), 290ns (BLANK = float), 375ns (BLANK = 3V8) - supports high-frequency, high-input-voltage operation with short conduction periods. |
Pinout & Package
Package: 24-lead narrow plastic SSOP (GN24), 0.25mm lead pitch, exposed PGND pad (Pin 25) requiring PCB soldering for thermal and electrical performance (θJA = 85°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DMAX (Pin 1) | Maximum duty cycle programming | SGND = 96%, float = 84%, 3V8 = 75% - sets hard limit on on-time to prevent instability at high VIN/VOUT ratios. |
| PHASEMODE (Pin 4) | Interleaving phase configuration | SGND/float/3V8 selects CH1–CH2 phase offset (180°/180°/120°) and CH1–CLKOUT relationship (90°/60°/240°) for multi-phase expansion. |
| GATE1/GATE2 (Pins 18/16) | N-channel MOSFET gate drivers | 10V rail-referenced outputs (–0.3V to 11V abs max); RDS(ON) = 3Ω pull-up / 0.9Ω pull-down - directly drives high-QG MOSFETs. |
| SENSE1+/SENSE2+ (Pins 23/13) | Current sense positive inputs | Differential inputs to current comparators; trip threshold adjustable via ITH voltage (65–85mV typical) - enables precise peak current limiting. |
| INTVCC (Pin 19) | 10V gate driver LDO output | Bypass with ≥4.7µF X5R ceramic to PGND; UVLO protection prevents weak gate drive - critical for reliable MOSFET turn-on. |
| 3V8 (Pin 24) | 3.8V analog/digital LDO output | Bypass with 1nF ceramic to SGND; powers internal op-amps, comparators, and logic - isolated from PGND to minimize noise coupling. |
| PGND (Pin 17 + Exposed Pad 25) | Power ground return | Must be connected to MOSFET source nodes and INTVCC bypass cap - electrically isolated from SGND to separate high-current and signal paths. |
| SGND (Pin 9) | Signal ground reference | Return for FB, SS, ITH, RUN, and 3V8 bypass - kelvin-connected to output capacitor negative terminal for optimal load regulation. |
Key Features
| Feature | Design Value |
|---|---|
| Two-phase interleaved operation | Reduces input/output capacitor RMS current by ~30%, enabling smaller, lower-cost bulk capacitance in high-power boost designs. |
| Programmable slope compensation (SLOPE pin) | Normalized gain selectable as 0.625× (SGND), 1.0× (float), or 1.66× (3V8) - stabilizes current mode control across varying duty cycles and inductors. |
| Adjustable leading edge blanking (BLANK pin) | Configurable minimum on-time (210/290/375ns) - suppresses gate-drive-induced sensing noise during MOSFET turn-on. |
| Multi-phase synchronization (SYNC/CLKOUT/PHASEMODE) | Enables seamless scaling to 2-, 3-, 4-, 6-, or 12-phase systems without external timing components - simplifies high-current power supply design. |
| Precision RUN pin with hysteresis | 1.22V enable threshold with 80mV hysteresis and programmable pull-up (0.5µA → 5µA) - provides clean, noise-immune start-up sequencing. |
Applications
| Telecom Power Supply | Industrial Motor Drive Bias |
|---|---|
|
Use Scenario: Generating stable 48V or 80V bias rails from 12V/24V intermediate bus in 4G/5G base station RF power amplifiers. IC Role / Device Role / Timing Role: Two-phase boost controller regulating output voltage via FB loop while synchronizing to system clock via SYNC pin. Use Value: Interleaving cuts input ripple current by 50%, allowing smaller input capacitors and meeting stringent EMI Class B limits. |
Use Scenario: Providing isolated gate drive voltage for high-side IGBTs in servo motor inverters using SEPIC topology with wide input variation (18–36V). IC Role / Device Role / Timing Role: Constant-frequency current-mode SEPIC controller with programmable DMAX and slope compensation for stability under load transients. Use Value: 96% max duty cycle enables reliable 60V output from 24V min input; 1.223V reference ensures ±1% output accuracy over temperature. |
| Automotive ADAS Camera Power | Test Equipment High-Voltage Source |
|
Use Scenario: Powering 70V image sensors in automotive surround-view cameras from 9–16V battery supply with cold-crank immunity down to 5.5V. IC Role / Device Role / Timing Role: Dual-phase boost controller with 4.4V INTVCC UVLO+ ensuring gate drive remains active during battery dips. Use Value: BLANK pin configuration minimizes false current-sense triggering during cranking transients, preventing unwanted shutdown. |
Use Scenario: Programmable high-voltage DC source (up to 100V) in automated test equipment requiring precise, low-noise output with fast transient response. IC Role / Device Role / Timing Role: Precision feedback-controlled boost controller using external resistive divider and soft-start (SS pin) for controlled ramp-up. Use Value: ±1% reference and <0.01%/V feedback line regulation maintain output accuracy across input voltage changes during dynamic loading. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar boost/SEPIC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC3862EUH-2#PBF | Same die, 5mm × 5mm QFN package (θJA = 44°C/W vs. 85°C/W for SSOP); identical pinout except PGND pad layout. | Better thermal performance enables higher continuous output current in space-constrained layouts; requires different PCB land pattern. | Select when thermal headroom is limited and board area permits QFN footprint; not drop-in compatible due to package and thermal pad differences. |
| LTC3862EFE-2#PBF | Same die, 24-lead TSSOP package (θJA = 38°C/W); identical electrical specs and pin mapping to SSOP variant. | Slightly better thermal resistance than SSOP; same lead pitch (0.65mm) but larger body size - eases hand-soldering and rework. | Prefer for prototyping or low-volume production where thermal margin exceeds SSOP capability but QFN assembly is impractical. |
Compared with LTC3862EGN-2#PBF, the QFN variant offers superior thermal performance for high-power density designs, while the TSSOP variant provides easier manufacturability and moderate thermal improvement - both retain identical control functionality and pin-level compatibility except for package-specific mechanical interfaces.
Availability
LTC3862EGN-2#PBF is available at Aetrix Electronics and suitable for telecom power supplies, industrial motor drive bias circuits, automotive ADAS camera modules, and test equipment high-voltage sources requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for LTC3862EGN-2#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and power management ICs, serving industrial, automotive, communications, and aerospace markets.
The LTC3862 family was designed specifically for high-efficiency, multi-phase boost and SEPIC DC/DC conversion in demanding power systems - emphasizing precision control, thermal robustness, and flexible phase expansion.
FAQ
What is the operating temperature range for the LTC3862EGN-2#PBF?
The LTC3862EGN-2#PBF is rated for –40°C to +85°C junction temperature (E-grade). Its absolute maximum junction temperature is 150°C, and thermal resistance θJA is 85°C/W in the 24-lead narrow SSOP package. Derating is required above 125°C to ensure reliability, and PCB layout must include proper thermal vias under the exposed PGND pad.
How does the PHASEMODE pin affect multi-phase operation of the LTC3862EGN-2#PBF?
The PHASEMODE pin on the LTC3862EGN-2#PBF configures the phase relationship between Channel 1 and Channel 2 (180°/180°/120°) and between Channel 1 and CLKOUT (90°/60°/240°). When used with SYNC and CLKOUT pins across multiple LTC3862EGN-2#PBF units, it enables deterministic 2-, 3-, 4-, 6-, or 12-phase interleaving without external timing ICs.
Can the LTC3862EGN-2#PBF drive logic-level MOSFETs?
The LTC3862EGN-2#PBF is optimized for 6V-VGS rated high-voltage N-channel MOSFETs, with INTVCC UVLO thresholds (4.4V/3.9V) aligned to that requirement. While it can drive logic-level devices, its 10V gate drive and UVLO settings do not fully exploit their low-threshold advantage - for dedicated logic-level support, consult the LTC3862 data sheet for alternate variants.
What is the purpose of the 3V8 pin on the LTC3862EGN-2#PBF?
The 3V8 pin on the LTC3862EGN-2#PBF is the output of an internal 3.8V LDO powered from INTVCC. It supplies low-noise power to internal analog circuitry (error amplifier, comparators, references) and digital logic. It must be bypassed with a 1nF ceramic capacitor to SGND and is not intended for external loads.
How is the switching frequency set on the LTC3862EGN-2#PBF?
The switching frequency of the LTC3862EGN-2#PBF is set by a resistor (RFREQ) from the FREQ pin to SGND, supporting 75kHz to 500kHz. The nominal FREQ pin voltage is 1.223V. Alternatively, the device can synchronize to an external clock (50–650kHz) applied to the SYNC pin, aligning GATE1 edges to the SYNC rising edge via its internal PLL.
LTC3862EGN-2#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 24-SSOP (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Up, Step-Up/Step-Down
- Output Configuration:
- Positive
- Topology:
- Boost, SEPIC
- Number of Outputs:
- 2
- Output Phases:
- 2
- Voltage - Supply (Vcc/Vdd):
- 5.5V ~ 36V
- Frequency - Switching:
- 75kHz ~ 500kHz
- Duty Cycle (Max):
- 96%
- Synchronous Rectifier:
- No
- Clock Sync:
- Yes
- Serial Interfaces:
- -
- Control Features:
- Enable, Frequency Control, Phase Control, Soft Start
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-SSOP
LTC3862EGN-2#PBF FAQ
1.How can I place an order for LTC3862EGN-2#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3862EGN-2#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3862EGN-2#PBF reliable?
The price and inventory of LTC3862EGN-2#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3862EGN-2#PBF is usually 5 days.
3.What payment methods are accepted for LTC3862EGN-2#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3862EGN-2#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3862EGN-2#PBF?
LTC3862EGN-2#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3862EGN-2#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3862EGN-2#PBF?
For technical support, including LTC3862EGN-2#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3862EGN-2#PBF requirements.
6.How does Aetrix verify that LTC3862EGN-2#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3862EGN-2#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3862EGN-2#PBF meets industry standards.
7.What is the process for return or replacement of LTC3862EGN-2#PBF?
All LTC3862EGN-2#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3862EGN-2#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3862EGN-2#PBF part is unused and in its original packaging.
Return procedure for LTC3862EGN-2#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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