Analog Devices Inc. LTC3862EUH-1#PBF

Overview

LTC3862EUH-1#PBF from Analog Devices (formerly Linear Technology) is a two-phase, constant-frequency, peak current mode boost/SEPIC DC/DC controller driving N-channel MOSFETs for high-voltage step-up conversion. It operates from 8.5V to 36V input, delivers up to 96% duty cycle, supports 75kHz–500kHz adjustable switching frequency, and integrates dual 10V gate drivers and cascaded 10V/3.8V LDOs - used in telecom power supplies generating 72V outputs from 24V rails.

For engineers reviewing the LTC3862EUH-1#PBF datasheet, LTC3862EUH-1#PBF pinout, LTC3862EUH-1#PBF application, or LTC3862EUH-1#PBF equivalent, key selection considerations include phase synchronization capability (SYNC/CLKOUT/PHASEMODE), programmable leading-edge blanking (BLANK pin), slope compensation gain control (SLOPE pin), maximum duty cycle configuration (DMAX pin), and thermal performance of the 5mm × 5mm QFN package with exposed PGND pad.

Technical Context

The LTC3862EUH-1#PBF implements fixed-frequency, peak current mode control with two independent channels operating 180° out of phase. Its error amplifier compares FB voltage against a ±1% 1.223V internal reference, generating ITH voltage to set peak inductor current. Slope compensation (via SLOPE pin) stabilizes operation under low-duty-cycle or high-input-voltage conditions.

Phase-lock loop (PLL) synchronization enables precise multi-phase coordination across 2-, 3-, 4-, 6-, or 12-phase systems using SYNC input and CLKOUT output. Internal 10V INTVCC LDO powers gate drivers with UVLO (7.5V rising, 7.0V falling); 3.8V 3V8 LDO supplies analog/digital circuitry. All critical thresholds - RUN (1.22V enable), DMAX (96%/84%/75%), BLANK (210/290/375ns min on-time) - are pin-programmable.

Key Specifications

Pinout & Package

The LTC3862EUH-1#PBF is housed in a 24-lead, 5mm × 5mm plastic QFN package (UH24) with 0.65mm lead pitch and thermally enhanced exposed PGND pad (Pin 25) that must be soldered to PCB ground for electrical integrity and thermal performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar boost/SEPIC controller applications.

Compared with LTC3862IUH-1#PBF and LTC3862HUH-1#PBF, the LTC3862EUH-1#PBF offers identical electrical performance and package but is optimized for cost-sensitive commercial-temperature applications; its 85°C upper limit simplifies thermal design in controlled environments while retaining full feature compatibility.

Availability

LTC3862EUH-1#PBF is available at Aetrix Electronics and suitable for telecom power supplies, industrial HV bias generators, automotive ADAS camera systems, and test equipment HV sources requiring stable component supply and long-term production continuity.

Supply support for LTC3862EUH-1#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices acquired Linear Technology in 2017 and maintains full product support, documentation, and manufacturing continuity for the LTC portfolio.

The LTC3862 family is designed specifically for high-efficiency, high-voltage, multi-phase boost and SEPIC DC/DC conversion - targeting applications where input-to-output voltage ratios exceed 2:1 and thermal management, EMI control, and precise output regulation are critical.

FAQ

What is the absolute maximum input voltage rating for the LTC3862EUH-1#PBF?

The LTC3862EUH-1#PBF has an absolute maximum input supply voltage (VIN) rating of 40V. Operation above this level risks permanent damage. The recommended operating range remains 8.5V to 36V per specifications, with thermal derating required near the upper limit due to increased power dissipation in the INTVCC LDO and gate drivers.

How does the BLANK pin affect minimum on-time in the LTC3862EUH-1#PBF?

The BLANK pin on the LTC3862EUH-1#PBF directly sets minimum on-time: connecting it to SGND yields 210ns, floating gives 290ns, and tying to 3V8 extends it to 375ns. This programmability prevents false triggering from gate-drive noise during MOSFET turn-on, especially critical in high-dV/dt boost topologies where sense signals are susceptible to coupling.

Can the LTC3862EUH-1#PBF synchronize to an external clock, and what is its valid frequency range?

Yes, the LTC3862EUH-1#PBF accepts external synchronization via the SYNC pin across 50kHz to 650kHz. The internal PLL locks to the rising edge of the external clock, aligning GATE1 timing precisely. This enables EMI reduction through frequency shifting and coordinated multi-phase operation without master-slave latency issues.

What is the purpose of the exposed pad (Pin 25) on the LTC3862EUH-1#PBF QFN package?

The exposed pad (Pin 25) on the LTC3862EUH-1#PBF is electrically connected to PGND and must be soldered to a PCB thermal pad. It reduces θJA to 44°C/W and provides the primary path for heat dissipation from the die - omitting this connection risks exceeding the 150°C maximum junction temperature under typical load conditions.

Does the LTC3862EUH-1#PBF support SEPIC topology, and what design considerations apply?

Yes, the LTC3862EUH-1#PBF supports SEPIC topology using both channels in complementary mode. Key considerations include configuring SENSE1+/SENSE1– for primary switch current sensing, ensuring proper transformer/coupled inductor selection for energy transfer, and verifying slope compensation (SLOPE pin) settings to maintain stability across the full duty cycle range required for SEPIC operation.