Analog Devices Inc. LTC3865IFE#PBF
- Part No.:
- LTC3865IFE#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 38-TFSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
LTC3865IFE#PBF.pdf
- Description:
- IC REG CTRLR BUCK 38TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,431
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC3865IFE#PBF from Analog Devices (formerly Linear Technology) is a dual, 2-phase synchronous step-down DC/DC controller driving all-N-channel MOSFET stages. It delivers precise 1.5V/15A and 1.2V/15A outputs with 180° phase interleaving, 4.5V–38V input range, and pin-selectable output voltages from 0.6V to 5V via VID strapping. Used in high-efficiency DC power distribution systems for FPGA, ASIC, and multi-rail server applications.
For engineers reviewing the LTC3865IFE#PBF datasheet, LTC3865IFE#PBF pinout, LTC3865IFE#PBF application, or LTC3865IFE#PBF equivalent, this page provides verified package mapping (38-lead TSSOP), confirmed dual-phase current-mode operation, OPTI-LOOP® compensation support, independent track/soft-start control per channel, and real-world efficiency data up to 95% at full load.
Technical Context
The LTC3865IFE#PBF implements a constant-frequency current-mode architecture with phase-lockable oscillator (250kHz–770kHz) and dual 180° out-of-phase controllers to minimize input/output ripple and EMI. Each channel features independent error amplifiers, ITH-based current threshold control, and programmable current foldback via ILIM pin.
It supports RSENSE or DCR current sensing, selectable operating modes (Burst Mode®, pulse-skipping, continuous conduction) via MODE/PLLIN, and robust protection including output overvoltage lockout (±10%), reverse current limiting, and undervoltage lockout on INTVCC (3.3V with 0.55V hysteresis).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5V to 38V - supports wide industrial and telecom input rails without external pre-regulation. |
| Output Voltage Range | 0.6V to 5V - set precisely via 2-pin VID strapping per channel, enabling discrete voltage rails for core/I/O domains. |
| Switching Frequency | 250kHz to 770kHz - adjustable via FREQ pin current (7.5μA) and external resistor; phase-lockable for system synchronization. |
| Efficiency | Up to 95% - achieved using dual N-channel synchronous drive, low RDS(on) gate drivers (TG RUP = 2.6Ω, BG RDOWN = 1.4Ω), and optimized light-load modes. |
| Current Sensing | RSENSE or DCR - flexible sensing with programmable max sense threshold (22–84mV depending on ILIM state) and ±1μA sense pin bias. |
| Thermal Performance | θJA = 25°C/W (TSSOP) - enables high-power dual-output regulation up to 125°C junction temperature with minimal heatsinking. |
| Soft-Start Control | 1.3μA internal charge current on TK/SS pins - allows linear output ramping or precise voltage tracking between channels. |
Pinout & Package
Package: 38-lead plastic TSSOP (FE package), exposed pad (Pin 39) tied to SGND for thermal and signal integrity. Requires soldering of exposed pad to PCB ground plane.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RUN1, RUN2 (Pins 1, 17) | Channel Enable Inputs | Independent shutdown control; >1.22V enables channel, <1.1V disables; includes 1μA pull-up and 4.5μA active pull-up. |
| TK/SS1, TK/SS2 (Pins 6, 12) | Tracking/Soft-Start Inputs | Internal 1.3μA current charges external capacitor for controlled VOUT ramp; also accepts resistor-divided reference for supply tracking. |
| VID11, VID12, VID21, VID22 (Pins 9, 10, 18, 37) | Output Voltage Programming Inputs | Binary-coded strapping pins (GND/INTVCC/float) selecting 9 discrete output voltages from 0.602V to 5.075V per channel. |
| ILIM (Pin 19) | Current Sense Threshold Select | Configures max sense voltage (22/42/66mV for I-grade) by tying to SGND/FLOAT/INTVCC - sets current limit sensitivity per channel. |
| PGOOD1, PGOOD2 (Pins 20, 21) | Dedicated Power-Good Outputs | Open-drain indicators asserting low when respective VOUT deviates >±10%; includes 100μs blanking after startup or fault. |
| MODE/PLLIN (Pin 36) | Operating Mode & Sync Input | Selects Burst Mode® (float), pulse-skip (INTVCC), or forced continuous (SGND); accepts external clock for PLL synchronization. |
| FREQ (Pin 38) | Oscillator Frequency Set | 7.5μA constant current source - external resistor to SGND sets frequency from 210kHz to 880kHz with ±10% tolerance. |
| SENSE1+/SENSE1−, SENSE2+/SENSE2− (Pins 2, 3, 15, 16) | Differential Current Sense Inputs | Accepts Kelvin-connected sense resistors or DCR networks; ±1μA input bias enables accurate low-side or high-side sensing. |
Key Features
| Feature | Design Value |
|---|---|
| Dual 180° phased controllers | Reduces input/output capacitor RMS current by ~30% and cuts peak-to-peak ripple amplitude vs single-phase designs. |
| OPTI-LOOP® compensation | Enables stable loop response across wide output capacitance (10μF–1000μF) and ESR (0.5mΩ–50mΩ) variations without redesign. |
| Independent track/soft-start | Allows staggered startup sequencing or exact voltage ramp matching between 1.5V and 1.2V rails for FPGA core/I/O compliance. |
| Adjustable current limit | Three-level ILIM selection (22/42/66mV) enables precise MOSFET SOA protection without external scaling components. |
| Output OV protection + reverse current limit | Prevents damage during hot-swap events or load dump; blocks reverse current flow during shutdown or fault conditions. |
| Power Good monitoring | Dual open-drain PGOOD outputs simplify system-level power sequencing and fault reporting in multi-rail architectures. |
Applications
| FPGA Core & I/O Power | Server CPU VRM |
|---|---|
Use Scenario: Supplying 1.5V core and 1.2V I/O rails to Xilinx Kintex-7 FPGA with tight transient response requirements. IC Role / Device Role / Timing Role: Dual-phase synchronous buck controller delivering coordinated, interleaved regulation with independent soft-start and tracking. Use Value: Eliminates need for two discrete controllers; reduces board area by 40% and input capacitance by 35% vs single-phase solutions. |
Use Scenario: Generating 1.2V/15A and 1.5V/15A for Intel Xeon E5 memory subsystem and PCIe switch logic. IC Role / Device Role / Timing Role: High-current, phase-interleaved DC/DC controller with programmable current foldback and PGOOD sequencing. Use Value: Achieves >94% efficiency at 12V input, meets Intel VR12.5 ripple specs (<10mVpp), and supports dynamic voltage scaling via VID. |
| Industrial PLC Power | Telecom Line Card |
Use Scenario: Providing isolated 1.2V and 1.5V supplies for ARM Cortex-A9 SoC and DDR3 memory in DIN-rail mounted PLC. IC Role / Device Role / Timing Role: Robust dual-output controller with wide 4.5V–38V input range and -40°C to 125°C operation. Use Value: Survives 48V DC bus transients; maintains regulation during brownouts; eliminates external UVLO circuitry. |
Use Scenario: Powering DSP, SerDes, and PHY ICs on 3.3V/12V telecom line cards requiring low-noise, high-density conversion. IC Role / Device Role / Timing Role: Dual-phase controller with Burst Mode® for standby efficiency and phase-lock for EMI reduction. Use Value: Reduces no-load power to <30μA; achieves <10mVpp output noise at 770kHz switching; passes EN55022 Class B. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-phase synchronous buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP8765GL-10-Z | Single-chip dual-phase controller with integrated 40V/5A MOSFETs; fixed 600kHz frequency; no VID programming or ILIM select. | Lower component count but limited to ≤12V input and ≤15A total output; lacks independent tracking and PGOOD per rail. | Choose MP8765GL-10-Z for cost-sensitive, lower-power applications where integration outweighs configurability. |
| ISL95812IRZ | Intel VR12.5-compliant dual-phase controller with SMBus interface; supports adaptive voltage positioning (AVP); no Burst Mode®. | Designed specifically for CPU VRMs with dynamic VID updates; requires external PMBus host; higher quiescent current (5mA). | Choose ISL95812IRZ only for Intel CPU platforms requiring AVP and digital telemetry; not suitable for generic FPGA/ASIC rails. |
Compared with MP8765GL-10-Z and ISL95812IRZ, the LTC3865IFE#PBF offers broader input range (4.5–38V), true independent dual-rail control with VID/ILIM/TK-SS flexibility, and superior light-load efficiency via Burst Mode®, making it optimal for non-CPU, multi-domain industrial and telecom power systems.
Availability
LTC3865IFE#PBF is available at Aetrix Electronics and suitable for FPGA power delivery, server VRM design, and industrial PLC power systems requiring stable component supply, long-term lifecycle support, and guaranteed -40°C to 125°C operation.
Supply support for LTC3865IFE#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and power management semiconductors.
The LTC3865IFE#PBF belongs to Linear's high-efficiency DC/DC controller product line, engineered for demanding multi-rail power systems in computing, communications, and industrial equipment where precision, reliability, and thermal performance are critical.
FAQ
What is the maximum supported switching frequency for the LTC3865IFE#PBF?
The LTC3865IFE#PBF supports a phase-lockable oscillator frequency range of 250kHz to 770kHz. The upper limit of 770kHz is achieved when the FREQ pin is biased with a resistor ≤325kΩ. This high-frequency capability enables compact magnetics and reduced output capacitance in space-constrained designs while maintaining stability via OPTI-LOOP® compensation.
Does the LTC3865IFE#PBF support independent enable/disable of each output channel?
Yes, the LTC3865IFE#PBF provides fully independent channel control via RUN1 (Pin 1) and RUN2 (Pin 17). Pulling either pin below 1.1V disables its associated controller and gate drivers while leaving the other channel operational. This enables flexible power sequencing, fault isolation, and dynamic rail shutdown in multi-domain systems.
How does the ILIM pin affect current limiting on the LTC3865IFE#PBF?
The ILIM pin (Pin 19) configures the maximum current sense threshold for both channels: tying to SGND selects 22mV, floating selects 42mV, and tying to INTVCC selects 66mV (I-grade). This directly scales the peak inductor current limit without external resistors, enabling precise MOSFET SOA protection tailored to specific FET RDS(on) and layout parasitics.
Can the LTC3865IFE#PBF be used with DCR current sensing?
Yes, the LTC3865IFE#PBF fully supports DCR current sensing via its differential SENSE1+/SENSE1− and SENSE2+/SENSE2− inputs. The ±1μA input bias current and low offset allow accurate sensing across typical PCB trace or inductor DCR values (0.5mΩ–10mΩ), eliminating the need for lossy sense resistors and improving full-load efficiency.
What is the purpose of the MODE/PLLIN pin on the LTC3865IFE#PBF?
The MODE/PLLIN pin (Pin 36) serves dual functions: selecting operating mode (Burst Mode® when floating, pulse-skip when tied to INTVCC, forced continuous when grounded) and accepting an external clock for phase synchronization. This enables EMI reduction via frequency dithering or system-level timing alignment in multi-controller environments.
LTC3865IFE#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 38-TFSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Number of Outputs:
- 2
- Output Phases:
- 2
- Voltage - Supply (Vcc/Vdd):
- 4.5V ~ 38V
- Frequency - Switching:
- 250kHz ~ 770kHz
- Duty Cycle (Max):
- 95%
- Synchronous Rectifier:
- Yes
- Clock Sync:
- No
- Serial Interfaces:
- -
- Control Features:
- Current Limit, Enable, Frequency Control, Power Good, Soft Start, Tracking
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 38-TSSOP-EP
LTC3865IFE#PBF FAQ
1.How can I place an order for LTC3865IFE#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3865IFE#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3865IFE#PBF reliable?
The price and inventory of LTC3865IFE#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3865IFE#PBF is usually 5 days.
3.What payment methods are accepted for LTC3865IFE#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3865IFE#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3865IFE#PBF?
LTC3865IFE#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3865IFE#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3865IFE#PBF?
For technical support, including LTC3865IFE#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3865IFE#PBF requirements.
6.How does Aetrix verify that LTC3865IFE#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3865IFE#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3865IFE#PBF meets industry standards.
7.What is the process for return or replacement of LTC3865IFE#PBF?
All LTC3865IFE#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3865IFE#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3865IFE#PBF part is unused and in its original packaging.
Return procedure for LTC3865IFE#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC3865IFE#PBF Tags

-
UCC28C45DR
Texas Instruments

-
UCC28C40DR
Texas Instruments

-
UCC28C43DR
Texas Instruments

-
ZXSC410E6TA
Diodes Incorporated
-
LM3524DMX/NOPB
Texas Instruments
-
LM3489MMX/NOPB
Texas Instruments

-
MIC2102YML-TR
Microchip Technology

-
LM5148RGYR
Texas Instruments
-
TL598CDR
Texas Instruments

-
LM5155DSSR
Texas Instruments

-
LM25085MYX/NOPB
Texas Instruments

-
UCC2813DTR-0
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

