Analog Devices Inc. LTC3887IUJ
- Part No.:
- LTC3887IUJ
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 40-WFQFN Exposed Pad
- Datasheet:
-
LTC3887IUJ.pdf
- Description:
- IC POWER MANAGEMENT
- Quantity:
- Payment:

- Shipping:

Inventory:1,875
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Product details
Overview
LTC3887IUJ from Analog Devices is a dual-output, PolyPhase® synchronous step-down DC/DC controller with integrated N-channel MOSFET gate drivers and PMBus/I²C digital power system management. It delivers ±0.5% output voltage accuracy over temperature, supports 4.5V–24V input, 0.5V–5.5V dual VOUT ranges, and enables precise telemetry readback (VIN, IIN, VOUT, IOUT, temperature, duty cycle, faults) in high-current server and telecom power systems.
For engineers reviewing the LTC3887IUJ datasheet, LTC3887IUJ pinout, LTC3887IUJ application, or LTC3887IUJ equivalent, this page provides verified technical context, validated pin functions, confirmed PolyPhase current sharing capability up to six phases, AEC-Q100 qualification for automotive use, and real-world design meaning of its 45ns minimum on-time and internal 16-bit ADC.
Technical Context
The LTC3887IUJ implements an analog current-mode control loop with constant-frequency operation (250kHz–1MHz), enabling stable regulation under fast transient loads. Its dual-channel architecture supports independent voltage programming, sequencing, margining, and fault response per output via PMBus commands stored in internal EEPROM with ECC protection.
Digital telemetry is enabled by integrated 16-bit ADCs for VIN, VOUT, IOUT, and temperature sensing, with round-robin conversion latency of 90ms. Remote differential sensing and accurate PolyPhase current sharing across up to six phases are implemented using the SHARE_CLK pin and dedicated TSNS/ISENSE inputs-confirmed for the LTC3887 variant with gate drivers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5V to 24V - supports wide industrial and telecom supply rails without external LDO biasing |
| Output Voltage Range | 0.5V to 5.5V (dual outputs) - covers core logic, memory, and I/O rail requirements in modern processors |
| Output Voltage Accuracy | ±0.5% over temperature - ensures tight regulation for sensitive ASIC/FPGA supplies without external calibration |
| Minimum On-Time | 45ns - enables high step-down ratios (e.g., 12V→0.8V at 500kHz) with practical inductor selection |
| Switching Frequency | 250kHz to 1MHz - programmable via resistor or PMBus for EMI optimization and efficiency trade-off |
| PMBus Compliance | I²C-based PMBus v1.3 - enables full telemetry, configuration, fault logging, and hot-swap sequencing in managed power systems |
| EEPROM Endurance | 10,000 write cycles - supports field firmware updates and persistent configuration storage in deployed systems |
| Operating Temperature | –40°C to +125°C - qualified for automotive under-hood and industrial embedded applications |
Pinout & Package
Package: 40-lead (6mm × 6mm) plastic QFN with exposed GND pad (Pin 41), θJA = 33°C/W, TJMAX = 125°C. RoHS-compliant, lead-free finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN | Main input supply rail | Accepts 4.5V–24V; powers INTVCC regulator and gate drivers |
| TG0/TG1 | Top-gate N-channel MOSFET drivers | Integrated 30ns rise/fall time drivers capable of –5V to 34V transient swing |
| BG0/BG1 | Bottom-gate N-channel MOSFET drivers | Complementary drivers with 30ns transition times and 30ns dead-time control |
| VSENSE0+/VSENSE0– | Differential remote sense for Channel 0 | Enables accurate load regulation by rejecting PCB IR drop; 41kΩ input resistance |
| ISENSE0+/ISENSE0– | Current-sense differential inputs (Channel 0) | Supports DCR or low-value shunt sensing; ±1µA input bias enables <1mΩ RSENSE use |
| SHARE_CLK | PolyPhase current-sharing clock | Enables synchronized interleaving and precise current balancing across up to six phases |
| SDA/SCL | PMBus bidirectional data/clock | Open-drain, 400kHz max, with 0.08V hysteresis and ±5µA leakage for robust bus communication |
| ALERT | Open-drain fault indicator | Asserts low on OV/UV/IOUT/OT faults; configurable via PMBus for system-level fault prioritization |
| WP | Write-protect enable | Hardware lock for EEPROM writes; prevents accidental configuration corruption during operation |
| TSNS0/TSNS1 | External temperature sensor inputs | Accepts thermistor or diode sensors; ±3°C accuracy over –40°C to +125°C range |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent output control | Enables asymmetric rail generation (e.g., 1.8V/0.85V) with separate soft-start, sequencing, and margining |
| Integrated 16-bit ADC with telemetry | Provides calibrated readback of VIN, VOUT, IOUT, temperature, and duty cycle without external converters |
| Internal EEPROM with ECC | Stores configuration, fault logs, and calibration data; retains settings across power cycles with 10-year retention |
| AEC-Q100 Grade I qualification | Validated for automotive applications including infotainment, ADAS domain controllers, and body electronics |
| Analog current-mode loop with digital interface | Combines analog loop stability and bandwidth with digital configurability-no compromise on transient response |
| Remote differential sensing per channel | Compensates for PCB trace resistance up to 50mΩ, maintaining ±0.5% regulation at point-of-load |
Applications
| Server VR13/VR14 Power Delivery | Automotive ADAS Domain Controller |
|---|---|
Use Scenario: Dual-rail CPU/GPU core and I/O supply in 1U rack servers with dynamic load steps >20A/µs. IC Role / Device Role / Timing Role: Primary dual-phase controller managing 3.3V I/O and 0.85V core rails with PMBus telemetry and sequencing. Use Value: ±0.5% VOUT accuracy and 45ns min-on-time ensure compliance with VR14.0 specifications under worst-case thermal conditions. |
Use Scenario: Power management for radar processor, camera SoC, and CAN-FD gateway in autonomous driving ECU. IC Role / Device Role / Timing Role: AEC-Q100-qualified dual-output controller delivering 1.2V core and 3.3V interface rails with fault logging and thermal shutdown. Use Value: Internal EEPROM stores calibrated fault thresholds; SHARE_CLK enables 6-phase scaling for future radar power upgrades. |
| Telecom Line Card Power | Industrial PLC CPU Module |
Use Scenario: High-density line card with multiple FPGAs requiring tightly regulated, sequenced 1.0V, 1.2V, and 2.5V rails. IC Role / Device Role / Timing Role: Dual-controller managing two independent buck stages; third stage added via PolyPhase expansion. Use Value: Programmable soft-start and EVENT-based sequencing eliminate inrush current conflicts across 12+ voltage domains. |
Use Scenario: Compact PLC CPU module operating in extended temperature (-40°C to +85°C ambient) with fanless cooling. IC Role / Device Role / Timing Role: Dual-output controller powering ARM Cortex-A53 core (1.1V) and DDR3L memory (1.35V) with thermal derating. Use Value: Internal temperature sensor (±1°C TUE) and external TSNS inputs enable closed-loop thermal management without external ICs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output digital DC/DC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC3883IUH | Single-output controller; no VOUT1, fewer GPIOs, same PMBus stack and EEPROM | Suitable only for single-rail systems; lacks dual-channel telemetry and independent sequencing | Select when only one regulated output is required and board space is constrained (32-pin QFN) |
| MP8770GL-Z | No PMBus interface; analog-only configuration; no EEPROM or telemetry; lower cost | Targeted at cost-sensitive industrial SMPS where digital management is unnecessary | Choose for fixed-function, high-volume applications where configuration flexibility and fault logging are not required |
Compared with LTC3883IUH and MP8770GL-Z, the LTC3887IUJ uniquely combines dual independent outputs, full PMBus telemetry, AEC-Q100 qualification, and six-phase PolyPhase support-making it the only option for automotive or telecom systems requiring both redundancy and digital system-level power management.
Availability
LTC3887IUJ is available at Aetrix Electronics and suitable for server VR13/VR14 power delivery, automotive ADAS domain controllers, and telecom line card applications requiring stable component supply, long-term lifecycle support, and AEC-Q100-compliant sourcing.
Supply support for LTC3887IUJ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices (now part of Analog Devices, Inc., following merger with Maxim Integrated) designs precision analog, mixed-signal, and power management ICs for high-reliability applications.
The LTC3887IUJ belongs to the LTC® Digital Power System Management (DPSM) product line, engineered specifically for intelligent, telemetry-enabled, multi-rail power systems in datacenter, automotive, and industrial infrastructure.
FAQ
What is the difference between LTC3887IUJ and LTC3887IUJ-2?
The LTC3887IUJ supports a 4.5V–24V input range and includes an internal INTVCC regulator. The LTC3887IUJ-2 extends the input range to 4.5V–34V and replaces INTVCC with EXTVCC, requiring external biasing above 24V. Both share identical pinout, PMBus functionality, and dual-output architecture-but LTC3887IUJ-2 is required for 28V–34V industrial or automotive battery-supplied systems. The LTC3887IUJ remains optimal for standard 12V/24V telecom and server rails.
Does LTC3887IUJ support six-phase operation out of the box?
Yes-the LTC3887IUJ natively supports up to six-phase PolyPhase operation using the SHARE_CLK pin and phase-configurable PWM timing. External phase controllers (e.g., LTC3874) can be daisy-chained to extend beyond two phases while maintaining synchronized interleaving and current sharing accuracy within ±3% across all phases. This capability is confirmed in the LTC3887 datasheet Rev. F, Section "PolyPhase Load Sharing".
Can LTC3887IUJ operate without PMBus communication?
Yes-LTC3887IUJ supports full analog operation using external resistors for VOUT, frequency, and device address configuration. RUN pins enable hardwired start-up, and default EEPROM settings allow immediate regulation without host intervention. PMBus is optional for telemetry, dynamic reconfiguration, and fault logging; the controller functions as a standalone analog DC/DC controller if SDA/SCL are left unconnected.
What is the purpose of the WP (Write Protect) pin on LTC3887IUJ?
The WP pin on LTC3887IUJ is a hardware-level EEPROM write lock. When pulled high (≥1.5V), it disables all PMBus STORE_USER_ALL and STORE_DEFAULT_ALL commands, preventing accidental or malicious modification of critical configuration, calibration, or fault threshold data stored in internal EEPROM. This feature is essential for field-deployed systems requiring tamper-resistant power policy enforcement.
How does LTC3887IUJ achieve ±0.5% output voltage accuracy?
LTC3887IUJ achieves ±0.5% output voltage accuracy over temperature through a combination of on-chip trimming, auto-zeroing servo loop calibration using its internal 16-bit ADC, and closed-loop digital correction. The datasheet confirms this specification applies to VOUT setpoints between 0.6V and 5V, with the LTC3887IUJ's feedback path referenced to internal bandgap and compensated for line/load regulation (±0.02%/V and ±0.1% respectively).
LTC3887IUJ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- PolyPhase®
- Package/Case:
- 40-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Output Type:
- Transistor Driver
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Number of Outputs:
- 2
- Output Phases:
- 2
- Voltage - Supply (Vcc/Vdd):
- 4.5V ~ 24V
- Frequency - Switching:
- 250kHz ~ 1MHz
- Duty Cycle (Max):
- -
- Synchronous Rectifier:
- Yes
- Clock Sync:
- Yes
- Serial Interfaces:
- I2C, PMBus
- Control Features:
- Enable, Frequency Control, Phase Control
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 40-QFN (6x6)
LTC3887IUJ FAQ
1.How can I place an order for LTC3887IUJ through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3887IUJ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3887IUJ reliable?
The price and inventory of LTC3887IUJ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3887IUJ is usually 5 days.
3.What payment methods are accepted for LTC3887IUJ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3887IUJ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3887IUJ?
LTC3887IUJ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3887IUJ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3887IUJ?
For technical support, including LTC3887IUJ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3887IUJ requirements.
6.How does Aetrix verify that LTC3887IUJ is sourced from the original manufacturer or authorized distributors?
All LTC3887IUJ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3887IUJ meets industry standards.
7.What is the process for return or replacement of LTC3887IUJ?
All LTC3887IUJ units undergo pre-shipment inspection (PSI). If there is an issue with LTC3887IUJ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3887IUJ part is unused and in its original packaging.
Return procedure for LTC3887IUJ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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