Analog Devices Inc. LTC3899EFE#TRPBF
- Part No.:
- LTC3899EFE#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 38-TFSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
LTC3899EFE#TRPBF.pdf
- Description:
- IC REG CTRLR BCK/BCK-BST 38TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC3899EFE#TRPBF from Analog Devices (formerly Linear Technology) is a high-performance triple-output synchronous buck/buck/boost DC/DC controller driving all-N-channel MOSFET stages. It operates from 4.5V to 60V input, delivers up to 60V output on boost channel, supports phase-lockable switching up to 850kHz, and achieves 29μA no-load quiescent current - enabling cold-crank operation down to 2.2V in automotive start-stop systems.
For engineers reviewing the LTC3899EFE#TRPBF datasheet, LTC3899EFE#TRPBF pinout, LTC3899EFE#TRPBF application, or LTC3899EFE#TRPBF equivalent, key selection criteria include its triple-output topology with independent run control, OPTI-LOOP® compensation for wide capacitor/ESR tolerance, programmable gate drive (5–10V), and dual-package availability (38-lead TSSOP and QFN) with exposed thermal pad.
Technical Context
The LTC3899EFE#TRPBF implements constant-frequency current-mode control across three independent channels: two synchronous buck controllers (Channels 1 & 2) and one synchronous boost controller (Channel 3). Each channel features dedicated ITH error amplifier inputs, SENSE+/- current-sense terminals, and RUN pins for individual enable/disable control.
Its architecture integrates internal top-gate bootstrap switches (eliminating external diodes), OPTI-DRIVE™ gate voltage programming via DRVSET, and a dual-source DRVCC LDO (selectable between VBIAS and EXTVCC). The PLLIN/MODE pin enables either external clock synchronization or selectable light-load modes (Burst Mode, pulse-skipping, or forced continuous).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5V to 60V main supply; supports 2.2V cold-crank operation after startup when biased from boost output or auxiliary rail. |
| Output Topology | Triple-output: two synchronous buck channels + one synchronous boost channel; all drive external N-channel MOSFETs. |
| Switching Frequency | Programmable 50kHz–900kHz; phase-lockable 75kHz–850kHz via PLLIN/MODE pin. |
| Quiescent Current | 29μA in Sleep Mode (one channel active); 3.6μA in full shutdown - critical for always-on automotive systems. |
| Feedback Accuracy | Buck: ±0.8% over temperature (0.792V–0.812V); Boost: ±1.5% (1.182V–1.218V at VPRG3 = float). |
| Gate Drive Voltage | Programmable 5V–10V via DRVSET pin; eliminates need for external level-shifting or discrete gate drivers. |
| Package | 38-lead TSSOP (LTC3899EFE#TRPBF) with exposed GND pad; θJA = 25°C/W; rated for –40°C to +125°C junction. |
Pinout & Package
Package: 38-lead plastic TSSOP (FE package), 5mm × 7mm footprint, exposed thermal pad (Pin 39 = GND, must be soldered to PCB). Thermal resistance θJA = 25°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FREQ (Pin 1) | Oscillator frequency control | Resistor-to-GND sets 50–900kHz; GND = 350kHz, INTVCC = 535kHz; enables precise frequency tuning without external clock. |
| PLLIN/MODE (Pin 2) | Synchronization & light-load mode select | Accepts external clock for phase-locking; also selects Burst Mode (GND/floating), pulse-skipping (1.1–INTVCC−1.3V), or forced CCM (INTVCC). |
| RUN1/RUN2/RUN3 (Pins 9/10/11) | Independent channel enable | Each pin controls one regulator; <1.2V disables channel; all <0.7V forces full shutdown (3.6μA IQ). |
| DRVSET (Pin 16) | DRVCC LDO output voltage programming | GND = 6V, INTVCC = 10V, resistor divider = 5–10V; also selects UVLO thresholds and EXTVCC switchover points. |
| VPRG3 (Pin 34) | Boost output configuration | Float = adjustable (via VFB3 feedback); GND = fixed 10V; INTVCC = fixed 12V - simplifies design for common boost voltages. |
Key Features
| Feature | Design Value |
|---|---|
| OPTI-LOOP® Compensation | Allows stable loop response across wide range of output capacitance (10µF–1000µF) and ESR (0.5mΩ–100mΩ), reducing design iterations. |
| No External Bootstrap Diodes | Integrated high-side driver switches eliminate discrete diodes and associated layout complexity and failure points. |
| 100% Duty Cycle Support (Boost) | Enables seamless regulation even when VIN ≥ VOUT (e.g., 12V input → 10V regulated output), critical for battery backup systems. |
| 99% Duty Cycle (Buck) | Supports ultra-low dropout operation - maintains regulation with VIN only ~1% above VOUT, extending usable input range. |
| Independent Channel Control | Three RUN pins allow staggered startup, fault isolation, and dynamic power sequencing in multi-rail systems. |
Applications
| Automotive Start-Stop Systems | Distributed Power Architectures |
|---|---|
Use Scenario: Maintaining stable 5V and 8.5V rails during engine cranking where battery voltage dips to 2.2V. IC Role / Device Role / Timing Role: Triple-output controller managing buck-buck-boost conversion with cold-crank resilience and low-IQ sleep mode. Use Value: Eliminates need for separate pre-regulators or backup capacitors; extends microcontroller uptime during transient brownouts. | Use Scenario: Generating isolated 5V, 8.5V, and 10V outputs from a shared 24V or 48V intermediate bus in telecom or industrial equipment. IC Role / Device Role / Timing Role: Centralized multi-output controller replacing three discrete regulators, synchronized via PLLIN/MODE. Use Value: Reduces board area by >40% vs discrete solutions; enables coordinated soft-start and fault response across rails. |
| Multi-Rail FPGA/ASIC Power | Battery-Powered Telematics |
Use Scenario: Powering core (0.85V), I/O (1.8V), and auxiliary (3.3V/5V) rails for FPGAs requiring precise sequencing and tight regulation. IC Role / Device Role / Timing Role: Buck/buck/boost controller delivering three independently regulated outputs with TRACK/SS1/SS2/SS3 sequencing capability. Use Value: Enables accurate voltage ramp alignment using external resistor dividers; avoids costly PMICs with limited flexibility. | Use Scenario: Long-life portable diagnostic tools powered by Li-ion (3.0–4.2V) requiring 5V USB, 8.5V display backlight, and 10V sensor bias. IC Role / Device Role / Timing Role: High-efficiency triple-output controller operating from single-cell battery with 29μA sleep IQ and programmable gate drive. Use Value: Extends runtime >3× vs standard controllers; 5–10V gate drive optimizes FET RDS(on) for both logic- and standard-level MOSFETs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple-output synchronous controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC3855EUFD#TRPBF | Dual-output buck-only controller (no boost); 32-pin QFN; max 40V input; no cold-crank support below 4.5V. | Cannot replace LTC3899EFE#TRPBF in boost-required or sub-4.5V cold-crank applications. | Select only if system requires only dual buck outputs and operates strictly above 4.5V input. |
| MP2918GL-Z | Triple-output buck/buck/buck (no boost); 40V input; integrated MOSFETs; no programmable gate drive or cold-crank capability. | Not suitable for boost-dependent loads (e.g., 10V sensor bias); lacks 2.2V cold-crank operation and external FET flexibility. | Consider only for space-constrained, lower-power (<3A/channel) buck-only designs where integration outweighs topology limitations. |
Compared with LTC3855EUFD#TRPBF and MP2918GL-Z, the LTC3899EFE#TRPBF uniquely combines triple-output buck/buck/boost topology, 2.2V cold-crank support, programmable gate drive, and independent RUN control - making it the sole option for automotive multi-rail systems requiring regulated boost output under extreme input transients.
Availability
LTC3899EFE#TRPBF is available at Aetrix Electronics and suitable for automotive start-stop systems, distributed DC power architectures, multi-rail FPGA/ASIC power supplies, and battery-powered telematics requiring stable component supply, long-term lifecycle support, and AEC-Q200-aligned reliability.
Supply support for LTC3899EFE#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its high-performance analog and power management portfolio with rigorous automotive and industrial qualification standards.
The LTC3899 product line was designed specifically for demanding multi-output DC/DC conversion in automotive, industrial, and telecom applications where cold-crank resilience, ultra-low quiescent current, and flexible topology are mandatory.
FAQ
What is the minimum input voltage for LTC3899EFE#TRPBF during cold-crank operation?
The LTC3899EFE#TRPBF supports cold-crank operation down to 2.2V input after startup - but only when biased from the boost output or an auxiliary supply. Its nominal input range remains 4.5V to 60V from the VBIAS pin. This 2.2V capability is enabled by internal biasing architecture and verified in the datasheet's "Cold Crank" application note (Figure TA01a).
Does LTC3899EFE#TRPBF integrate bootstrap diodes for high-side gate drive?
No, the LTC3899EFE#TRPBF does not require external bootstrap diodes. It integrates internal switches in the top-gate drivers (TG1/TG2/TG3) that automatically charge the BOOST capacitors during each switching cycle - eliminating discrete diodes, reducing BOM count, and improving reliability in high-vibration environments like automotive systems.
Can LTC3899EFE#TRPBF generate a fixed 10V boost output without external resistors?
Yes. By connecting the VPRG3 pin (Pin 34) to GND, the LTC3899EFE#TRPBF configures Channel 3 for fixed 10V boost output - using an internal reference instead of external feedback resistors. This simplifies design, improves accuracy (±1.5%), and reduces component count versus adjustable configurations.
What is the thermal performance difference between the TSSOP and QFN packages of LTC3899EFE#TRPBF?
The LTC3899EFE#TRPBF uses the 38-lead TSSOP (FE) package with θJA = 25°C/W. Its QFN variant (LTC3899EUHF#TRPBF) has θJA = 34°C/W due to larger exposed pad area and superior PCB copper spreading. Both packages share identical electrical specs and pinout; thermal choice depends on board layout constraints and cooling capability - TSSOP suits legacy through-hole-compatible designs, QFN enables higher power density.
How does the OPTI-LOOP® compensation in LTC3899EFE#TRPBF simplify stability design?
The OPTI-LOOP® compensation in LTC3899EFE#TRPBF dynamically adjusts loop gain based on output capacitor ESR and value - allowing stable operation across 10µF–1000µF ceramic or polymer capacitors with ESR from 0.5mΩ to 100mΩ. This eliminates iterative compensation network tuning and enables robust performance across diverse output filter implementations without redesign.
LTC3899EFE#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 38-TFSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck, Buck-Boost
- Number of Outputs:
- 3
- Output Phases:
- 2
- Voltage - Supply (Vcc/Vdd):
- 4.5V ~ 60V
- Frequency - Switching:
- 105kHz ~ 835kHz, 350kHz ~ 535kHz
- Duty Cycle (Max):
- 100%
- Synchronous Rectifier:
- Yes
- Clock Sync:
- No
- Serial Interfaces:
- -
- Control Features:
- Enable, Frequency Control, Soft Start, Tracking
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 38-TSSOP-EP
LTC3899EFE#TRPBF FAQ
1.How can I place an order for LTC3899EFE#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3899EFE#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3899EFE#TRPBF reliable?
The price and inventory of LTC3899EFE#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3899EFE#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC3899EFE#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3899EFE#TRPBF transactions.
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4.How is shipping managed for LTC3899EFE#TRPBF?
LTC3899EFE#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3899EFE#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3899EFE#TRPBF?
For technical support, including LTC3899EFE#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3899EFE#TRPBF requirements.
6.How does Aetrix verify that LTC3899EFE#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC3899EFE#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3899EFE#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC3899EFE#TRPBF?
All LTC3899EFE#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3899EFE#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3899EFE#TRPBF part is unused and in its original packaging.
Return procedure for LTC3899EFE#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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