My Inquiry
My Account
Analog Devices Inc. LTC6090CFE#PBF
- Part No.:
- LTC6090CFE#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 16-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
LTC6090CFE#PBF.pdf
- Description:
- IC OPAMP GP 1 CIRCUIT 16TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:107
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC6090CFE#PBF from Analog Devices (formerly Linear Technology) is a high-voltage, precision CMOS rail-to-rail output operational amplifier optimized for ±70V (140V total) supply operation. It delivers 12MHz gain-bandwidth, 21V/µs slew rate, 50mA output drive, picoamp input bias current (50pA max), and 1.25mV max input offset voltage - enabling high-impedance buffering and high-gain signal conditioning in photodiode amplifiers, piezo drivers, and high-voltage DAC buffers.
For engineers reviewing the LTC6090CFE#PBF datasheet, LTC6090CFE#PBF pinout, LTC6090CFE#PBF application, or LTC6090CFE#PBF equivalent, key selection criteria include guaranteed 0°C to 70°C junction temperature range, TSSOP-16E thermally enhanced package with exposed V– pad, thermal warning flag (TFLAG), output disable (OD) control, and compatibility with ±4.75V to ±70V supplies while driving up to 200pF loads.
Technical Context
The LTC6090CFE#PBF implements a proprietary high-voltage CMOS input stage with guarded differential pair architecture and rail-to-rail output stage capable of sourcing/sinking 50mA. Its internal thermal protection triggers TFLAG at 145°C with 5°C hysteresis and forces full shutdown at 175°C.
It supports unity-gain stability (LTC6090 variant) and features low 11nV/√Hz input voltage noise density, 3.5µVP-P 0.1Hz–10Hz noise, and 130dB minimum CMRR - all specified over ±70V supplies. The COM pin enables safe interfacing to low-voltage logic by establishing a reference for OD and TFLAG signals.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | ±4.75V to ±70V (140V total); supports unbalanced split supplies and single-ended high-side configurations. |
| Input Bias Current | 50pA maximum at ±70V; enables ultra-high-impedance sensor interfaces without significant DC error. |
| Input Offset Voltage | 1.25mV maximum; ensures <±125µV error in 100× gain stages at room temperature. |
| Gain-Bandwidth Product | 12MHz typical; supports stable closed-loop operation up to ~120kHz at AV = 100. |
| Slew Rate | 21V/µs typical; enables 100VP–P output swing within <5µs settling time (0.1%). |
| Output Drive | ±50mA continuous; drives capacitive loads up to 200pF while maintaining stability. |
| Thermal Warning Threshold | TFLAG activates at 145°C die temperature; provides early overtemperature indication before shutdown. |
Pinout & Package
The LTC6090CFE#PBF is housed in a 16-lead plastic TSSOP package with exposed pad (Pin 17), electrically connected to V– and requiring soldering to PCB for thermal performance (θJC = 10°C/W). Guard pins (2,3,6,7,10,11,13,15) support guard ring implementation around high-impedance inputs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 (COM) | Common reference node | Establishes logic-level ground reference for OD and TFLAG; must be tied to low-voltage system ground or floated (internal divider sets ~30% mid-supply). |
| Pins 2,3,6,7,10,11,13,15 (GUARD) | Guard ring terminals | Enable low-leakage guard rings around –IN/+IN; reduce board leakage and improve CMRR in high-impedance applications. |
| Pin 4 (–IN) | Inverting input | Operates from V– + 3V to V+ – 3V; protected by back-to-back diodes and current-limiting resistors. |
| Pin 5 (+IN) | Noninverting input | Same common-mode range as –IN; guarded layout recommended to minimize leakage-induced offset drift. |
| Pin 8 (V–) | Negative supply | Connect directly to negative rail; exposed pad (Pin 17) is internally bonded to V– and must be soldered to PCB ground plane. |
| Pin 9,17 (TFLAG) | Open-drain thermal flag | Sinks 200µA when die ≥145°C; requires external pull-up to COM or logic supply for active-low signaling. |
| Pin 12 (OUT) | Amplifier output | Rail-to-rail swing (±70V); avoid forward-biasing ESD diodes by limiting output beyond V+/V– rails. |
| Pin 14 (V+) | Positive supply | Accepts up to +70V; bypass with 0.1µF ceramic capacitor close to pin for stability. |
| Pin 16 (OD) | Active-low output disable | Pulled up internally (2MΩ); drives low (≤0.65V relative to COM) to disable output stage while preserving input bias. |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail output stage | Delivers ±70V swing into 10kΩ load with <500mV headroom; maintains linearity across full output range. |
| Thermal warning & shutdown | TFLAG alerts at 145°C; secondary shutdown at 175°C with 7°C hysteresis prevents irreversible junction damage. |
| Guard pin architecture | Eight dedicated guard pins enable complete guard ring enclosure of –IN/+IN nodes, reducing board leakage by >10×. |
| Low-noise precision performance | 3.5µVP-P (0.1–10Hz) and 11nV/√Hz (1kHz) noise support sub-picoamp photodiode current measurement. |
| Output disable with standby mode | OD pin reduces supply current to 580µA (typ) while keeping input stage active - ideal for power-gated systems. |
Applications
| Piezo Driver | Photodiode Amplifier |
|---|---|
Use Scenario: Driving high-capacitance piezoelectric actuators in precision positioning systems requiring ±100V excitation. IC Role / Device Role / Timing Role: High-voltage, low-noise transimpedance amplifier with rail-to-rail output and fast settling. Use Value: Delivers 21V/µs slew rate and 50mA drive to achieve <5µs step response for nanometer-resolution motion control. |
Use Scenario: Converting femtoamp photocurrents from avalanche photodiodes into measurable voltage signals. IC Role / Device Role / Timing Role: Ultra-low-input-bias-current transimpedance amplifier with guarded input structure. Use Value: 50pA max input bias and 3.5µVP-P low-frequency noise enable accurate detection of weak optical signals. |
| High-Voltage DAC Buffer | Optical Networking Transmitter |
Use Scenario: Buffering 16-bit DAC outputs in high-voltage power supply calibration circuits requiring ±70V compliance. IC Role / Device Role / Timing Role: Precision unity-gain stable buffer with low offset drift (±5µV/°C) and high PSRR (112dB). Use Value: Maintains <±1LSB error over temperature and supply variations in metrology-grade voltage references. |
Use Scenario: Biasing laser diodes and modulators in 100Gbps coherent optical transceivers with precise current/voltage control. IC Role / Device Role / Timing Role: High-speed, high-voltage driver for analog front-end control loops in CFP2/OSFP modules. Use Value: 12MHz GBW and 21V/µs slew rate support fast modulation waveforms while rejecting supply ripple. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-voltage precision op amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LT1490AIS8#PBF | Lower supply (±40V), higher input bias (250pA), no TFLAG/OD, SO-8 only | Limited to ≤±40V systems; lacks thermal monitoring and output disable for safety-critical HV designs | Select when cost-sensitive, lower-voltage (<±40V), and thermal management is handled externally. |
| OPA454IDDA | Higher supply (±50V), higher IB (10nA), no guard pins, DDA-8 package | Not suitable for ultra-high-Z photodiode apps; lacks guard architecture and TSSOP thermal enhancement | Choose for industrial motor control where 50mA drive and ±50V suffice but pA-level bias isn't required. |
Compared with LT1490AIS8#PBF and OPA454IDDA, the LTC6090CFE#PBF uniquely combines ±70V operation, 50pA input bias, integrated thermal flag, output disable, and TSSOP guard pins - making it the only option for precision, safety-aware, ultra-high-impedance 140V applications.
Availability
LTC6090CFE#PBF is available at Aetrix Electronics and suitable for photodiode amplifiers, piezo drivers, and high-voltage DAC buffers requiring stable component supply across industrial, test equipment, and optical networking programs.
Supply support for LTC6090CFE#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its legacy of high-performance analog ICs with rigorous process control and application-focused design.
The LTC6090CFE#PBF belongs to Linear's high-voltage precision op amp family, engineered specifically for applications demanding rail-to-rail output, picoamp input bias, and robust thermal protection in ±70V systems.
FAQ
What is the operating temperature range for the LTC6090CFE#PBF?
The LTC6090CFE#PBF is specified for a junction temperature range of 0°C to 70°C. This grade is validated for commercial applications and differs from the I-grade (–40°C to 85°C) and H-grade (–40°C to 125°C) variants. Thermal derating must be applied if ambient conditions exceed this range, using θJA = 57°C/W (typical with moderate PCB copper).
Does the LTC6090CFE#PBF require external compensation for unity-gain stability?
No - the LTC6090CFE#PBF is unity-gain stable by design. Unlike the LTC6090-5 variant (stable only at noise gain ≥5), the LTC6090CFE#PBF supports AV = 1 configurations without external compensation. Its phase margin exceeds 60° at unity gain with 10kΩ load and 50pF capacitance, per Figure G01 in the datasheet.
How is the COM pin used in low-voltage interface circuits with the LTC6090CFE#PBF?
The COM pin on the LTC6090CFE#PBF serves as the reference node for OD and TFLAG logic-level signaling. It should be tied to the low-voltage system ground (e.g., 3.3V or 5V domain) to ensure safe voltage levels between OD/COM and TFLAG/COM remain within –3V to +7V. If left floating, COM rises to ~30% of mid-supply due to internal resistive divider.
Can the LTC6090CFE#PBF drive capacitive loads up to 200pF without oscillation?
Yes - the LTC6090CFE#PBF is characterized to drive up to 200pF capacitive loads while maintaining stability under specified conditions (RL = 10kΩ, AV ≥ 1). Stability is ensured via internal compensation; however, layout best practices (short traces, local bypassing, guard rings) are essential to preserve phase margin in high-CL applications.
What is the function of the guard pins on the LTC6090CFE#PBF TSSOP package?
The eight guard pins (2,3,6,7,10,11,13,15) on the LTC6090CFE#PBF enable physical implementation of a guard ring around the –IN and +IN nodes. When driven at the same potential as the inputs (e.g., via unity-gain follower), they reduce PCB surface leakage currents by >10×, critical for maintaining low offset drift in picoamp-level photodiode and electrometer applications.
LTC6090CFE#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- General Purpose
- Number of Circuits:
- 1
- Output Type:
- Rail-to-Rail
- Slew Rate:
- 21V/µs
- Gain Bandwidth Product:
- 12 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 3 pA
- Voltage - Input Offset:
- 330 µV
- Current - Supply:
- 2.8mA
- Current - Output / Channel:
- -
- Voltage - Supply Span (Min):
- 9.5 V
- Voltage - Supply Span (Max):
- 140 V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP-EP
LTC6090CFE#PBF FAQ
1.How can I place an order for LTC6090CFE#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC6090CFE#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC6090CFE#PBF reliable?
The price and inventory of LTC6090CFE#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC6090CFE#PBF is usually 5 days.
3.What payment methods are accepted for LTC6090CFE#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC6090CFE#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC6090CFE#PBF?
LTC6090CFE#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC6090CFE#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC6090CFE#PBF?
For technical support, including LTC6090CFE#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC6090CFE#PBF requirements.
6.How does Aetrix verify that LTC6090CFE#PBF is sourced from the original manufacturer or authorized distributors?
All LTC6090CFE#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC6090CFE#PBF meets industry standards.
7.What is the process for return or replacement of LTC6090CFE#PBF?
All LTC6090CFE#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC6090CFE#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC6090CFE#PBF part is unused and in its original packaging.
Return procedure for LTC6090CFE#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC6090CFE#PBF Tags
-
LM358DT
STMicroelectronics
-
LM358DR
Texas Instruments
-
LM2904DR
Texas Instruments
-
LM358ADR
Texas Instruments
-
LM2904DGKR
Texas Instruments
-
LM324DR
Texas Instruments
-
MCP6006T-E/OT
Microchip Technology
-
MCP6006UT-E/OT
Microchip Technology
-
LM324PWR
Texas Instruments
-
LM2902PWR
Texas Instruments
-
LM2902DR
Texas Instruments
-
LM358P
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
