Analog Devices Inc. LTC6090HFE-5#PBF
- Part No.:
- LTC6090HFE-5#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 16-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
LTC6090HFE-5#PBF.pdf
- Description:
- IC OPAMP GP 1 CIRCUIT 16TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,006
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC6090HFE-5#PBF from Analog Devices (formerly Linear Technology) is a high-voltage, precision operational amplifier optimized for noise gain ≥5 configurations. It delivers ±70V output swing, 12MHz gain-bandwidth product, 21V/µs slew rate, and 50pA max input bias current - enabling high-impedance piezo driver and photodiode amplifier applications requiring rail-to-rail output and thermal fault management.
For engineers reviewing the LTC6090HFE-5#PBF datasheet, LTC6090HFE-5#PBF pinout, LTC6090HFE-5#PBF application, or LTC6090HFE-5#PBF equivalent, key selection criteria include guaranteed –40°C to 125°C operation, TFLAG thermal warning output, OD-controlled output disable, guard-pin-enabled PCB layout for leakage-sensitive nodes, and compatibility with ±70V supplies driving up to 200pF loads.
Technical Context
The LTC6090HFE-5#PBF uses a proprietary CMOS process supporting 140V total supply while maintaining picoamp input bias and low offset drift. Its internal architecture includes differential drive generation, 500Ω output enable path, die temperature sensing with 145°C activation threshold, and open-drain TFLAG output with 5°C hysteresis.
It features dedicated COM, OD, and TFLAG pins referenced to a user-defined low-voltage ground, enabling safe interfacing with microcontrollers. The FE package integrates eight guard pins to support guard-ring layouts that isolate high-impedance inputs from leakage paths - critical for photodiode and ATE applications where input currents below 100pA must be preserved.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Range | ±4.75V to ±70V (140V total); supports unbalanced split supplies like +100V/–40V without sequencing constraints |
| Gain-Bandwidth Product | 12MHz at AV = 5; enables stable closed-loop operation in high-gain, high-voltage sensor conditioning |
| Slew Rate | 21V/µs; sustains fast transient response in piezo actuator drivers without distortion |
| Input Bias Current | 50pA max at ±70V; preserves signal integrity in high-impedance photodiode and electrometer circuits |
| CMRR | 130dB min; rejects common-mode interference in noisy industrial power supply monitoring |
| Thermal Warning Threshold | TFLAG activates at 145°C die temperature with 5°C hysteresis; enables fail-safe shutdown coordination |
| Output Drive | ±50mA continuous; drives capacitive loads up to 200pF while maintaining stability in DAC buffer stages |
Pinout & Package
Package: 16-lead plastic TSSOP with exposed pad (Pin 17), thermally enhanced for θJC = 10°C/W. Exposed pad must be soldered to V– plane for thermal performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| COM (Pin 1) | Reference node for OD and TFLAG logic levels | Must be tied to low-voltage ground for safe interface with 3.3V/5V controllers; floating causes ~30% mid-supply bias |
| –IN (Pin 4) | Inverting input | Common-mode range V–+3V to V+–3V; guard pins (2,3,6,7,10,11,13,15) surround it to suppress leakage in photodiode amps |
| +IN (Pin 5) | Noninverting input | Same CMR as –IN; guard ring routing supported via adjacent guard pins |
| V– (Pin 8, Exposed Pad Pin 17) | Negative supply | Electrically connected to exposed pad; requires direct low-inductance connection to V– plane for thermal dissipation |
| TFLAG (Pin 9, Pin 17) | Open-drain thermal flag | Sinks 200µA typical when die ≥145°C; must stay within –3V to +7V relative to COM to avoid damage |
| OUT (Pin 12) | Amplifier output | Rail-to-rail stage capable of ±70V swing; forward-biasing ESD diodes above V+ or below V– must be avoided |
| V+ (Pin 14) | Positive supply | Accepts up to +70V; bypass capacitor required close to pin for stability |
| OD (Pin 16) | Active-low output disable | Pulled up internally by 2MΩ; ≤0.65V relative to COM disables output stage while preserving input bias |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail output stage | Delivers ±70V swing into 10kΩ load with <1V headroom, enabling full utilization of 140V supply in HV regulator feedback |
| Integrated thermal protection | Dual-stage safety: TFLAG warns at 145°C (5°C hysteresis), hard shutdown triggers at 175°C (7°C hysteresis) |
| Guard-pin architecture | Eight dedicated guard terminals allow PCB guard rings around inputs, reducing board leakage by >10× in humid environments |
| Low-noise precision core | 3.5µVP-P (0.1–10Hz) and 11nV/√Hz @1kHz support sub-mV-level signal amplification in optical networking receivers |
| Output disable with standby mode | OD pin reduces supply current to 580µA typical while retaining input bias and offset stability during idle periods |
Applications
| Piezo Actuator Driver | Photodiode Transimpedance Amplifier |
|---|---|
Use Scenario: Driving high-capacitance piezoelectric positioners in semiconductor lithography stages requiring nanometer resolution under ±70V excitation. IC Role / Device Role / Timing Role: High-voltage, low-noise op-amp configured as non-inverting amplifier with gain ≥5, sourcing/sinking ±50mA into 100nF+ loads. Use Value: 21V/µs slew rate ensures <2.5µs settling for 1V steps; guard pins minimize leakage-induced drift during long-hold positioning. | Use Scenario: Converting weak photocurrents (<1nA) from avalanche photodiodes in fiber-optic test equipment into measurable voltage signals. IC Role / Device Role / Timing Role: Transimpedance amplifier with guarded –IN and COM-referenced OD/TFLAG for low-noise, high-Z signal conditioning. Use Value: 50pA max input bias avoids signal corruption; 130dB CMRR rejects ambient EMI in lab-grade optical receivers. |
| High-Voltage DAC Buffer | ATE Power Supply Monitor |
Use Scenario: Buffering 16-bit DAC outputs in programmable HV power supplies where output must swing ±70V with <1.25mV offset error. IC Role / Device Role / Timing Role: Unity-gain stable buffer (LTC6090-5 variant) isolating DAC from reactive loads while maintaining DC accuracy. Use Value: ±1.25mV max offset and ±5µV/°C drift ensure <0.01% full-scale error across –40°C to 125°C operating range. | Use Scenario: Monitoring output voltage of ±70V industrial power rails in automated test equipment with real-time overtemperature flagging. IC Role / Device Role / Timing Role: Precision difference amplifier feeding ADC, with TFLAG output wired to system controller for predictive thermal throttling. Use Value: PSRR >112dB rejects supply ripple; TFLAG activation at 145°C provides 5°C margin before hard shutdown at 150°C junction limit. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-voltage precision op-amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC6090HFE#PBF | Unity-gain stable; lower GBW (12MHz vs 24MHz for -5 version); no minimum noise gain requirement | Better suited for unity-gain buffers and integrators; less optimal for high-gain photodiode amps needing phase margin >60° | Select when circuit requires AV = 1 stability and lower quiescent current (3.9mA vs 4.3mA) |
| OPA454IDDA | Single 100V op-amp; higher input bias (200pA typ); no TFLAG or OD pins; SO-8 only | Lacks thermal warning and output disable; guard pins absent; unsuitable for leakage-critical photodiode designs | Choose only for cost-sensitive, non-thermal-critical ±50V applications without guard requirements |
Compared with LTC6090HFE#PBF, the LTC6090HFE-5#PBF trades unity-gain stability for higher bandwidth and improved phase margin at AV ≥5 - making it superior for high-gain transimpedance stages. Versus OPA454IDDA, it adds thermal intelligence and leakage mitigation but at higher pin count and cost.
Availability
LTC6090HFE-5#PBF is available at Aetrix Electronics and suitable for high-voltage DAC buffering, piezo actuation, photodiode amplification, and ATE power monitoring requiring stable component supply across extended temperature ranges.
Supply support for LTC6090HFE-5#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its legacy of high-performance analog ICs with rigorous characterization and application-focused design.
The LTC6090 family was developed to address precision high-voltage signal conditioning in optical networking, semiconductor test, and industrial motion control - where rail-to-rail output, picoamp inputs, and thermal resilience are mandatory.
FAQ
What is the maximum safe supply voltage for the LTC6090HFE-5#PBF?
The absolute maximum total supply voltage (V+ to V–) for the LTC6090HFE-5#PBF is 150V. Operation at the rated 140V (±70V) is fully specified and characterized across –40°C to 125°C. Exceeding 150V risks permanent damage per Absolute Maximum Ratings. Derating is recommended for long-term reliability at elevated temperatures.
How does the TFLAG pin function on the LTC6090HFE-5#PBF?
The TFLAG pin on the LTC6090HFE-5#PBF is an open-drain output that sinks 200µA typical when the die temperature reaches 145°C. It remains active until the junction cools to 140°C due to 5°C hysteresis. When tied to the OD pin, it automatically disables the output stage - a key safety feature confirmed in the LTC6090HFE-5#PBF datasheet Figure 4.
Can the LTC6090HFE-5#PBF drive capacitive loads, and what is the limit?
Yes, the LTC6090HFE-5#PBF is specified to drive up to 200pF of capacitive load while maintaining stability in noise gain ≥5 configurations. This capability is validated in the datasheet's Small Signal Frequency Response plots (Figures G15–G18) and enables direct interfacing with piezo elements and long cables without external isolation resistors.
What is the purpose of the COM pin on the LTC6090HFE-5#PBF?
The COM pin on the LTC6090HFE-5#PBF establishes a local reference for OD and TFLAG logic thresholds. It must be tied to the low-voltage ground (e.g., MCU ground) to ensure safe 3.3V/5V interfacing. If left floating, COM rises to ~30% of mid-supply due to internal dividers - risking violation of the –3V to +7V OD/COM and TFLAG/COM voltage limits.
Does the LTC6090HFE-5#PBF require external compensation for stability?
No, the LTC6090HFE-5#PBF is internally compensated for stable operation at noise gains of 5 or greater. It does not require external compensation components. However, the standard LTC6090 (non-"-5") variant is unity-gain stable and uses different internal compensation - confirming the "-5" suffix denotes a distinct, higher-bandwidth compensation scheme for the LTC6090HFE-5#PBF.
LTC6090HFE-5#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- General Purpose
- Number of Circuits:
- 1
- Output Type:
- Rail-to-Rail
- Slew Rate:
- 37V/µs
- Gain Bandwidth Product:
- 24 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 3 pA
- Voltage - Input Offset:
- 330 µV
- Current - Supply:
- 2.8mA
- Current - Output / Channel:
- 90 mA
- Voltage - Supply Span (Min):
- 9.5 V
- Voltage - Supply Span (Max):
- 140 V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP-EP
LTC6090HFE-5#PBF FAQ
1.How can I place an order for LTC6090HFE-5#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC6090HFE-5#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC6090HFE-5#PBF reliable?
The price and inventory of LTC6090HFE-5#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC6090HFE-5#PBF is usually 5 days.
3.What payment methods are accepted for LTC6090HFE-5#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC6090HFE-5#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC6090HFE-5#PBF?
LTC6090HFE-5#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC6090HFE-5#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC6090HFE-5#PBF?
For technical support, including LTC6090HFE-5#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC6090HFE-5#PBF requirements.
6.How does Aetrix verify that LTC6090HFE-5#PBF is sourced from the original manufacturer or authorized distributors?
All LTC6090HFE-5#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC6090HFE-5#PBF meets industry standards.
7.What is the process for return or replacement of LTC6090HFE-5#PBF?
All LTC6090HFE-5#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC6090HFE-5#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC6090HFE-5#PBF part is unused and in its original packaging.
Return procedure for LTC6090HFE-5#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC6090HFE-5#PBF Tags

-
LM358DT
STMicroelectronics

-
LM358DR
Texas Instruments

-
LM2904DR
Texas Instruments

-
LM358ADR
Texas Instruments
-
LM2904DGKR
Texas Instruments
-
LM324DR
Texas Instruments

-
MCP6006T-E/OT
Microchip Technology

-
MCP6006UT-E/OT
Microchip Technology

-
LM324PWR
Texas Instruments

-
LM2902PWR
Texas Instruments
-
LM2902DR
Texas Instruments

-
LM358P
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

