Analog Devices Inc. LTC6090IFE#TRPBF
- Part No.:
- LTC6090IFE#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 16-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
LTC6090IFE#TRPBF.pdf
- Description:
- IC OPAMP GP 1 CIRCUIT 16TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC6090IFE#TRPBF from Analog Devices (formerly Linear Technology) is a high-voltage, precision rail-to-rail output CMOS operational amplifier optimized for ±70V (140V total) supply operation. It delivers 50mA output drive, 12MHz gain-bandwidth product, 21V/µs slew rate, and 3.5µVP-P 0.1Hz–10Hz noise - enabling high-impedance buffering and high-gain amplification in piezo drivers, photodiode front-ends, and high-voltage DAC output stages.
For engineers reviewing the LTC6090IFE#TRPBF datasheet, LTC6090IFE#TRPBF pinout, LTC6090IFE#TRPBF application, or LTC6090IFE#TRPBF equivalent, key selection criteria include guaranteed ±70V supply capability, picoamp input bias current (≤50pA), thermal warning flag (TFLAG) activation at 145°C, output disable (OD) control interface, and TSSOP-16E package with guard pins for leakage-sensitive layouts.
Technical Context
The LTC6090IFE#TRPBF implements a proprietary high-voltage CMOS process enabling rail-to-rail output swing while maintaining low input offset voltage (±1.25mV max), ultra-low input bias current (50pA max at ±70V), and high open-loop gain (>1000 V/mV). Its internal architecture includes differential input stage with ESD protection, guarded input routing (in TSSOP), and dedicated die temperature sensor feeding an open-drain TFLAG output.
It features dual-stage thermal protection: TFLAG asserts at 145°C with 5°C hysteresis, and hard thermal shutdown activates at 175°C. The OD pin provides active-low output disable with internal 2MΩ pull-up; when tied to TFLAG, it enables autonomous overtemperature output disable without external logic.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | ±4.75V to ±70V (140V total); supports unbalanced split supplies (e.g., +100V/–40V) and single-ended high-side configurations. |
| Input Bias Current | ≤50pA maximum at ±70V; enables stable DC coupling in >1GΩ impedance nodes like photodiode transimpedance amplifiers. |
| Output Drive | ±50mA continuous RMS; sufficient to drive 200pF capacitive loads directly without external buffers in piezo actuator interfaces. |
| Small-Signal Bandwidth | 12MHz gain-bandwidth product; supports closed-loop gains up to 100V/V with adequate phase margin (60°) at 10kΩ load. |
| Low-Frequency Noise | 3.5µVP-P (0.1Hz–10Hz); critical for precision DC-coupled measurement systems requiring sub-microvolt stability. |
| Thermal Protection | TFLAG active at 145°C (5°C hysteresis); secondary shutdown at 175°C ensures safe operation under sustained overload or poor heatsinking. |
| Rail-to-Rail Output | Swings within 10mV of V+ and V– under no load; maintains ≥450mV headroom at ±10mA sink/source, enabling full dynamic range utilization. |
Pinout & Package
Package: 16-lead plastic TSSOP with exposed pad (Pin 17 = V–), thermally enhanced for θJC = 10°C/W. Exposed pad must be soldered to PCB ground plane for thermal performance and electrical connection to V–.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 (COM) | Common reference node | Establishes logic-level reference for OD and TFLAG; must be tied to low-voltage ground or left floating (internal divider sets ~30% above mid-supply). |
| Pins 2,3,6,7,10,11,13,15 (GUARD) | Guard ring terminals | Enable PCB guard rings around high-impedance inputs (–IN/+IN) to reduce leakage and improve CMRR in humid/dusty environments. |
| Pins 4 (–IN), 5 (+IN) | Differential input terminals | Support common-mode range from V–+3V to V+–3V; protected by back-to-back diodes and Zeners limiting differential swing to ≤12V. |
| Pin 8 (V–), Pin 17 (Exposed Pad) | Negative supply terminal | Electrically connected; exposed pad requires direct soldering to V– plane for thermal management and low-impedance return path. |
| Pin 9 (TFLAG) | Open-drain thermal flag | Sinks 200µA typical when die temperature ≥145°C; compatible with 3.3V/5V logic via pull-up resistor; voltage limited to –3V to +7V vs COM. |
| Pin 12 (OUT) | Amplifier output | Rail-to-rail capable; avoid forward-biasing ESD diodes by limiting output beyond V– or V+; drives capacitive loads up to 200pF. |
| Pin 14 (V+) | Positive supply terminal | Accepts up to +70V; requires local 0.1µF ceramic bypass capacitor; sequencing tolerant for split-supply applications. |
| Pin 16 (OD) | Active-low output disable | Pulled up internally (2MΩ); drives output stage into high-Z state when ≤0.65V below COM; draws only 580µA standby current. |
Key Features
| Feature | Design Value |
|---|---|
| 140V total supply capability | Enables direct interfacing with industrial HV rails (e.g., ±70V piezo drivers, electrostatic actuators) without external level-shifting or charge pumps. |
| Guard pin architecture (TSSOP) | Eight dedicated guard pins allow full PCB guard ring implementation around –IN/+IN, reducing board leakage and improving long-term DC stability. |
| Thermal warning + shutdown | TFLAG provides early overtemperature alert at 145°C; automatic OD tie disables output before reaching 150°C junction limit, preventing reliability degradation. |
| Ultra-low input bias current | 50pA max at ±70V allows use in femtoampere-level photodiode and ion-sensor applications where input leakage dominates error budget. |
| Output disable with standby mode | OD pin reduces supply current to 580µA while preserving input bias and offset calibration, enabling rapid wake-up (<1µs) without re-stabilization delay. |
Applications
| Piezo Actuator Driver | Photodiode Transimpedance Amplifier |
|---|---|
Use Scenario: Driving high-capacitance piezoelectric elements (nF range) in precision positioning systems requiring fast settling and low distortion. IC Role / Device Role / Timing Role: High-voltage output buffer with 50mA drive and 21V/µs slew rate, configured as non-inverting amplifier with gain ≥10. Use Value: Full 140VP-P output swing enables maximum piezo displacement; 200pF load drive eliminates need for external MOSFET buffer stages. |
Use Scenario: Converting weak photocurrents (pA–nA) from low-light detectors into stable voltage signals for ADC digitization. IC Role / Device Role / Timing Role: Precision transimpedance amplifier with guarded inputs, ultra-low input bias current, and low 1/f noise. Use Value: 50pA max input bias prevents signal corruption in high-impedance (>1GΩ) feedback networks; 3.5µVP-P noise preserves SNR in low-light conditions. |
| High-Voltage DAC Output Buffer | Optical Network Bias Controller |
Use Scenario: Buffering precision DAC outputs (e.g., LTC2641) to ±70V rails for laser diode modulation or variable optical attenuator control. IC Role / Device Role / Timing Role: Unity-gain stable voltage follower with rail-to-rail output, low offset drift (±5µV/°C), and high PSRR (112dB). Use Value: Maintains DAC accuracy across temperature; 12MHz bandwidth supports fast step response for dynamic optical power adjustment. |
Use Scenario: Providing stable, low-noise bias voltages to avalanche photodiodes (APDs) and electro-absorption modulators (EAMs) in fiber-optic transceivers. IC Role / Device Role / Timing Role: Low-drift, low-noise high-voltage reference buffer with thermal monitoring for APD bias safety interlocks. Use Value: 1.25mV max offset and ±5µV/°C drift ensure stable APD gain control; TFLAG integration enables automatic bias shutdown on overheating. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-voltage precision op amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LT1490AIS8#PBF | Lower supply (±40V), higher input bias (250pA), no TFLAG/OD, SO-8 only | Limited to ≤80V applications; lacks thermal management features needed for sustained HV operation | Choose only for cost-sensitive, lower-voltage (<±40V), non-thermal-critical designs where guard pins and 140V support are unnecessary. |
| OPA454AIDDA | Higher supply (±40V), higher IB (10nA), no guard pins, no TFLAG, DDA-8 package | Not suitable for pA-level photodiode apps; lacks thermal flag and guard architecture for leakage-sensitive layouts | Select only when driving purely resistive loads <100pF at ≤80V, and thermal monitoring is handled externally. |
Compared with LT1490AIS8#PBF and OPA454AIDDA, LTC6090IFE#TRPBF uniquely combines 140V operation, picoamp input bias, integrated thermal flag, and TSSOP guard pins - making it the only option for precision, high-reliability, high-voltage analog signal conditioning where leakage, noise, and thermal safety are co-constrained.
Availability
LTC6090IFE#TRPBF is available at Aetrix Electronics and suitable for piezo driver circuits, photodiode amplifier modules, and high-voltage DAC buffer designs requiring stable component supply across industrial temperature ranges (–40°C to +85°C).
Supply support for LTC6090IFE#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, formed through the acquisition of Linear Technology in 2017.
The LTC6090IFE#TRPBF belongs to ADI's precision high-voltage op amp product line, engineered specifically for applications demanding rail-to-rail output, ultra-low input bias, and robust thermal management in ±70V systems.
FAQ
What is the maximum supply voltage rating for the LTC6090IFE#TRPBF?
The LTC6090IFE#TRPBF has an absolute maximum total supply voltage of 150V, with recommended operation up to ±70V (140V total). Operation beyond ±70V risks exceeding safe operating area limits and may trigger thermal shutdown. The device is characterized and guaranteed for performance across its full ±4.75V to ±70V range.
Does the LTC6090IFE#TRPBF support rail-to-rail input common-mode voltage?
No, the LTC6090IFE#TRPBF does not support rail-to-rail input common-mode voltage. Its specified input common-mode range is V–+3V to V+–3V (guaranteed by CMRR), meaning it cannot accept signals within 3V of either supply rail. This limitation protects the input stage and ensures specified offset and noise performance.
How does the TFLAG pin function on the LTC6090IFE#TRPBF?
The TFLAG pin on the LTC6090IFE#TRPBF is an open-drain output that sinks 200µA typical when the die temperature reaches 145°C. It features 5°C hysteresis, deactivating at 140°C. When tied to the OD pin, it automatically disables the output stage during overtemperature events - a key safety feature for high-power HV applications.
Can the LTC6090IFE#TRPBF drive capacitive loads, and what is the maximum supported value?
Yes, the LTC6090IFE#TRPBF is specified to drive up to 200pF of capacitive load while maintaining stability. This capability is validated in the datasheet under small-signal transient response and frequency compensation tests. For loads >200pF, external isolation resistors or feedback network adjustments are required to prevent peaking or oscillation.
What is the purpose of the GUARD pins on the LTC6090IFE#TRPBF TSSOP package?
The eight GUARD pins on the LTC6090IFE#TRPBF TSSOP package enable construction of a continuous PCB guard ring around the high-impedance –IN and +IN nodes. This reduces surface leakage currents, improves long-term DC stability in humid environments, and enhances CMRR - especially critical in photodiode and electrometer applications.
LTC6090IFE#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Amplifier Type:
- General Purpose
- Number of Circuits:
- 1
- Output Type:
- Rail-to-Rail
- Slew Rate:
- 21V/µs
- Gain Bandwidth Product:
- 12 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 3 pA
- Voltage - Input Offset:
- 330 µV
- Current - Supply:
- 2.8mA
- Current - Output / Channel:
- -
- Voltage - Supply Span (Min):
- 9.5 V
- Voltage - Supply Span (Max):
- 140 V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP-EP
LTC6090IFE#TRPBF FAQ
1.How can I place an order for LTC6090IFE#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC6090IFE#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC6090IFE#TRPBF reliable?
The price and inventory of LTC6090IFE#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC6090IFE#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC6090IFE#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC6090IFE#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC6090IFE#TRPBF?
LTC6090IFE#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC6090IFE#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC6090IFE#TRPBF?
For technical support, including LTC6090IFE#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC6090IFE#TRPBF requirements.
6.How does Aetrix verify that LTC6090IFE#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC6090IFE#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC6090IFE#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC6090IFE#TRPBF?
All LTC6090IFE#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC6090IFE#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC6090IFE#TRPBF part is unused and in its original packaging.
Return procedure for LTC6090IFE#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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