Analog Devices Inc. LTC6090IS8E#TRPBF
- Part No.:
- LTC6090IS8E#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 8-SOIC (0.154", 3.90mm Width) Exposed Pad
- Datasheet:
-
LTC6090IS8E#TRPBF.pdf
- Description:
- IC OPAMP GP 1 CIRCUIT 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC6090IS8E#TRPBF from Analog Devices (formerly Linear Technology) is a high-voltage, precision CMOS rail-to-rail output operational amplifier with unity-gain stability, ±70V supply capability, 12MHz gain-bandwidth product, 21V/µs slew rate, and 50pA max input bias current. It serves as a high-impedance buffer or high-gain amplifier in piezo drivers, photodiode front-ends, and high-voltage DAC output stages.
For engineers reviewing the LTC6090IS8E#TRPBF datasheet, LTC6090IS8E#TRPBF pinout, LTC6090IS8E#TRPBF application, or LTC6090IS8E#TRPBF equivalent, key selection criteria include guaranteed –40°C to 85°C operation, thermal warning flag (TFLAG), output disable (OD) control, SOIC-8E thermally enhanced package with exposed V– pad, and picoamp-level input bias for ultra-high-impedance signal conditioning.
Technical Context
The LTC6090IS8E#TRPBF uses a proprietary high-voltage CMOS process enabling rail-to-rail output swing up to ±70V while maintaining low offset drift (±5µV/°C) and low 0.1Hz–10Hz noise (3.5µVP-P). Its input stage features guarded MOSFET inputs with integrated ESD protection and current-limiting resistors.
It integrates die temperature sensing with open-drain TFLAG output active at 145°C and hysteresis of 5°C, plus an active-low OD pin that disables only the output stage-leaving input and bias circuits powered-reducing standby current to ~580µA. The COM pin establishes a reference for OD/TFLAG logic interfacing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | ±4.75V to ±70V (140V total); supports unbalanced split supplies (e.g., +100V/–40V) without sequencing concerns. |
| Input Bias Current | 50pA maximum at ±70V; enables stable DC coupling into >10GΩ sources like photodiodes or piezoelectric sensors. |
| Offset Voltage | 1.25mV maximum; ensures <±100µV error in 100× gain configurations over full industrial temperature range. |
| Slew Rate | 21V/µs; delivers full ±70V output swing in <7µs for fast high-voltage step responses. |
| Gain-Bandwidth Product | 12MHz; supports closed-loop gains up to ~120 at 100kHz while maintaining phase margin >60°. |
| Output Drive | ±50mA continuous sink/source; drives 200pF capacitive loads directly without external buffering. |
| Thermal Protection | TFLAG activates at 145°C with 5°C hysteresis; internal shutdown triggers at 175°C to prevent permanent damage. |
Pinout & Package
Package: 8-Lead Plastic SOIC with Exposed Pad (S8E), RoHS-compliant, junction-to-case thermal resistance θJC = 5°C/W. Exposed pad (Pin 9) is electrically connected to V– and must be soldered to PCB for thermal performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V– (Pin 4, Exposed Pad Pin 9) | Negative Supply Rail | Primary return path for power and heat; exposed pad must be connected to V– plane for thermal management. |
| OD (Pin 8) | Active-Low Output Disable | Drives output stage into high-Z state when ≤COM+0.65V; internal 2MΩ pull-up enables default operation if left open. |
| V+ (Pin 7) | Positive Supply Rail | Accepts up to +70V; requires local 0.1µF ceramic bypass capacitor near pin. |
| OUT (Pin 6) | Amplifier Output | Rail-to-rail capable (±70V swing); avoid forward-biasing ESD diodes by limiting voltage beyond rails. |
| TFLAG (Pin 5) | Open-Drain Thermal Flag | Sinks ≥70µA when die temperature ≥145°C; used to auto-disable OD or trigger system-level thermal response. |
| COM (Pin 1) | Logic Reference Node | Establishes common ground for OD/TFLAG interface to low-voltage logic; floats to ~30% above mid-supply if unconnected. |
| –IN (Pin 2) | Inverting Input | High-impedance node (V–+3V to V+–3V common-mode range); guard ring routing recommended for leakage-critical apps. |
| +IN (Pin 3) | Noninverting Input | Matches –IN specs; differential input capacitance is 5pF, common-mode capacitance is 9pF. |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail output stage | Delivers ±70V output swing into 10kΩ load with <500mV headroom, enabling full utilization of high-voltage rails. |
| Thermal warning & auto-shutdown | TFLAG + OD interconnection provides autonomous output disable at 145°C, preventing thermal runaway before 150°C junction limit. |
| Low 0.1Hz–10Hz noise | 3.5µVP-P enables precision DC-coupled amplification of slow-moving signals (e.g., strain gauges, thermopiles) without 1/f noise corruption. |
| Guarded input architecture | SOIC-8E layout supports guard ring implementation around inputs to reduce board leakage and improve >100dB CMRR at high common-mode voltages. |
| Robust input protection | Integrated back-to-back diodes, current-limiting resistors, and Zener clamps protect against ±12V differential transients and ESD events per IEC 61000-4-2 Level 2. |
Applications
| Piezo Driver | Photodiode Amplifier |
|---|---|
Use Scenario: Driving high-capacitance piezoelectric actuators in precision positioning systems requiring ±100V output swing and sub-millisecond settling. IC Role / Device Role / Timing Role: High-voltage, high-slew-rate buffer delivering charge to piezo capacitance while rejecting supply noise via 130dB CMRR. Use Value: 21V/µs slew rate achieves <7µs full-scale step response; 200pF load drive eliminates need for external follower stage. | Use Scenario: Transimpedance amplification of low-current photodiode signals (<1nA) in optical receivers or spectrometers. IC Role / Device Role / Timing Role: Ultra-low-input-bias op-amp converting photocurrent to voltage with minimal dark-current error and low 1/f noise. Use Value: 50pA max input bias ensures <0.5% error at 10nA photocurrent; 11nV/√Hz noise density preserves SNR in bandwidth-limited detection. |
| High-Voltage DAC Buffer | Optical Networking Bias Control |
Use Scenario: Buffering 16-bit DAC outputs in programmable high-voltage power supplies (e.g., laser diode bias, ion trap control). IC Role / Device Role / Timing Role: Precision gain-stage isolating DAC from load while maintaining linearity across ±70V output range. Use Value: 1.25mV max offset and ±5µV/°C drift ensure <0.01% FSR error over temperature; rail-to-rail output avoids clipping at extremes. | Use Scenario: Providing stable, low-noise bias voltage to avalanche photodiodes (APDs) in fiber-optic transceivers operating at 10–25Gbps. IC Role / Device Role / Timing Role: Low-noise, high-PSRR voltage reference buffer rejecting switching noise from nearby DC/DC converters. Use Value: 112dB min PSRR suppresses 100kHz–1MHz supply ripple; 3.5µVP-P 0.1–10Hz noise prevents baseline wander in APD current monitoring. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-voltage precision op-amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| OPA454IDDA | Higher 100V supply rating but lower 2.5MHz GBW and 10V/µs slew rate; no TFLAG or OD pins. | Lacks integrated thermal management and output disable; requires external circuitry for safe shutdown. | Choose OPA454IDDA only when >±70V operation is mandatory and thermal autonomy is handled externally. |
| ADA4700-1ARMZ | Lower ±50V supply range; 10MHz GBW; 12V/µs slew; includes enable pin but no thermal flag. | Not suitable for ±70V systems; limited output drive (±20mA) restricts capacitive load handling. | Select ADA4700-1ARMZ for cost-sensitive ±50V designs where full LTC6090IS8E#TRPBF performance is unnecessary. |
Compared with OPA454IDDA and ADA4700-1ARMZ, the LTC6090IS8E#TRPBF uniquely combines ±70V operation, 12MHz bandwidth, thermal flag, and output disable in a single SOIC-8E package-enabling simpler, safer, and higher-performance high-voltage analog signal chains.
Availability
LTC6090IS8E#TRPBF is available at Aetrix Electronics and suitable for piezo driver modules, photodiode front-ends, high-voltage DAC buffers, optical networking bias supplies, and ATE test equipment requiring stable component supply across industrial temperature ranges.
Supply support for LTC6090IS8E#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, formed through the acquisition of Linear Technology in 2017.
The LTC6090IS8E#TRPBF belongs to ADI's Linear Technology high-voltage precision op-amp family, engineered for applications demanding wide supply range, ultra-low input bias, and robust thermal protection in compact packages.
FAQ
What is the operating temperature range for the LTC6090IS8E#TRPBF?
The LTC6090IS8E#TRPBF is specified for operation from –40°C to +85°C (industrial grade). This range is guaranteed for all electrical parameters including input offset voltage, bias current, and gain-bandwidth product. The device includes thermal protection that activates at 145°C die temperature, and absolute maximum junction temperature is 150°C.
Can the LTC6090IS8E#TRPBF drive capacitive loads up to 200pF without instability?
Yes, the LTC6090IS8E#TRPBF is designed to drive up to 200pF of capacitive load while maintaining stability. Its unity-gain stable architecture and internal compensation ensure phase margin remains >60° under this condition. For optimal performance, use short, direct traces to the load and maintain proper power supply decoupling with 0.1µF ceramic capacitors placed close to V+ and V– pins.
How does the COM pin function in the LTC6090IS8E#TRPBF?
The COM pin on the LTC6090IS8E#TRPBF serves as the reference node for the OD and TFLAG pins, enabling safe interfacing with low-voltage logic (e.g., 3.3V or 5V microcontrollers). When tied to low-voltage ground, it defines the logic thresholds for OD (active low ≤COM+0.65V) and TFLAG (open-drain sink). If left floating, COM rises to ~30% above mid-supply due to internal resistive divider.
What happens to the output stage when the OD pin is asserted on the LTC6090IS8E#TRPBF?
When the OD pin is pulled low (≤COM+0.65V), the LTC6090IS8E#TRPBF disables only its output stage while keeping the input and bias circuitry fully powered. This reduces quiescent supply current to ~580µA (typical) and places the OUT pin in high-impedance state. The amplifier resumes normal operation within microseconds after OD is released, as input and bias circuits remain active during disable.
Is the exposed pad on the LTC6090IS8E#TRPBF electrically connected, and how should it be handled?
Yes, the exposed pad (Pin 9) on the LTC6090IS8E#TRPBF is electrically connected to the V– supply rail. It must be soldered to a PCB copper area tied to V– for effective thermal dissipation. Recommended practice includes using multiple thermal vias (≥6x 0.3mm) from the pad to an internal or bottom-layer V– plane. Failure to connect the pad degrades θJA from 33°C/W to >100°C/W, risking thermal shutdown under load.
LTC6090IS8E#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Amplifier Type:
- General Purpose
- Number of Circuits:
- 1
- Output Type:
- Rail-to-Rail
- Slew Rate:
- 21V/µs
- Gain Bandwidth Product:
- 12 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 3 pA
- Voltage - Input Offset:
- 330 µV
- Current - Supply:
- 2.8mA
- Current - Output / Channel:
- -
- Voltage - Supply Span (Min):
- 9.5 V
- Voltage - Supply Span (Max):
- 140 V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC-EP
LTC6090IS8E#TRPBF FAQ
1.How can I place an order for LTC6090IS8E#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC6090IS8E#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC6090IS8E#TRPBF reliable?
The price and inventory of LTC6090IS8E#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC6090IS8E#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC6090IS8E#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC6090IS8E#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC6090IS8E#TRPBF?
LTC6090IS8E#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC6090IS8E#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC6090IS8E#TRPBF?
For technical support, including LTC6090IS8E#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC6090IS8E#TRPBF requirements.
6.How does Aetrix verify that LTC6090IS8E#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC6090IS8E#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC6090IS8E#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC6090IS8E#TRPBF?
All LTC6090IS8E#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC6090IS8E#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC6090IS8E#TRPBF part is unused and in its original packaging.
Return procedure for LTC6090IS8E#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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