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Analog Devices Inc. LTC6912CDE-1#TRPBF

Part No.:
LTC6912CDE-1#TRPBF
Manufacturer:
Analog Devices Inc.
Category:
Special Purpose Amplifiers
Package:
12-WFDFN Exposed Pad
Datasheet:
AetrixLTC6912CDE-1#TRPBF.pdf
Description:
IC OPAMP PGA 2 CIRCUIT 12DFN
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Payment
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Product details

Overview

LTC6912CDE-1#TRPBF from Analog Devices (formerly Linear Technology) is a dual-channel, digitally programmable gain amplifier (PGA) with independent 3-wire SPI-controlled gain selection across eight discrete inverting voltage gains: 0, 1, 2, 5, 10, 20, 50, and 100 V/V. It features rail-to-rail input/output operation, 2 mV max offset voltage over –40°C to 85°C, 0.1 dB max channel-to-channel gain matching, and 12.6 nV/√Hz input voltage noise density at 50 kHz. It is used in precision data acquisition systems requiring dynamic range optimization and automatic gain control.

For engineers reviewing the LTC6912CDE-1#TRPBF datasheet, LTC6912CDE-1#TRPBF pinout, LTC6912CDE-1#TRPBF application, or LTC6912CDE-1#TRPBF equivalent, key selection criteria include guaranteed gain accuracy at high settings (e.g., ±0.2 dB at G=100), hardware shutdown capability (2 µA max at 2.7 V), DFN-12 package thermal performance (θJA = 160°C/W), and compatibility with single-supply (2.7 V to 5.5 V) or dual-supply (±2.5 V) configurations.

Technical Context

The LTC6912CDE-1#TRPBF implements two matched, low-noise, inverting amplifiers sharing a common AGND reference node generated internally for single-supply operation. Gain is set via an 8-bit SPI register per channel, where bits Q3–Q0 define the gain code and Q7–Q4 are reserved or unused (per Table 1). All gains are inverting; no non-inverting configuration is supported.

Its architecture enables wired-OR analog multiplexing by connecting OUTA and OUTB externally, and supports software shutdown (state 1000) and hardware shutdown via SHDN pin (GN-16 only - not applicable to DFN-12). The device maintains >10 MΩ input resistance at gain = 0 or shutdown state, dropping to 1 kΩ at G = 100, with output impedance scaling linearly from 0.4 Ω (G = 0) to 30 Ω (G = 100).

Key Specifications

ParameterValue and Actual Design Meaning
Gain Options0, 1, 2, 5, 10, 20, 50, 100 V/V - all inverting; enables precise signal scaling without external feedback networks
Offset Voltage≤2 mV (–40°C to 85°C) - ensures DC accuracy in sensor front-ends and weigh-scale applications
Channel Matching≤0.1 dB gain mismatch - critical for differential measurements and ratiometric signal processing
Input Noise Density12.6 nV/√Hz at 50 kHz (G = 100) - supports high-resolution 18+ bit ADC interfacing with minimal SNR degradation
Supply Range2.7 V to 10.5 V total (single or dual) - operates from 3 V logic rails up to ±5 V supplies
Shutdown Current≤255 µA per channel (software), ≤2 µA total (hardware, GN-16 only) - enables ultra-low-power sleep modes
Package12-lead (4 mm × 3 mm) plastic DFN with exposed pad soldered to V– - provides low thermal resistance (θJA = 160°C/W)

Pinout & Package

12-lead DFN package (4 mm × 3 mm) with exposed thermal pad connected to V– (Pin 13, not counted in 12-pin count); requires PCB soldering of exposed pad for thermal and electrical integrity.

Pin/TerminalCircuit RoleDesign Meaning
1 (OUTA)Inverting amplifier A outputDrives load with rail-to-rail swing; compatible with wired-OR with OUTB
2 (V–)Negative supply / thermal pad connectionMust be soldered to PCB ground plane; defines lower rail and thermal path
3 (OUTB)Inverting amplifier B outputDrives load independently; enables dual-channel or multiplexed output routing
4 (V+)Positive supplyAccepts 2.7 V to 5.5 V (single) or +2.5 V to +5.5 V (dual); powers both channels
5 (DGND)Digital ground referenceReference for SPI interface signals (CS/LD, DIN, CLK, DOUT); must be tied to system digital ground
6 (DOUT)SPI serial data outputReads back register status; supports daisy-chaining multiple LTC6912 devices
7 (INA)Amplifier A inverting inputHigh-impedance node (10 kΩ at G = 1); accepts rail-to-rail input signals
8 (AGND)Analog ground / internal referenceInternally generated half-supply reference; must be decoupled with 1 µF capacitor
9 (INB)Amplifier B inverting inputMatched to INA; supports independent gain programming and signal routing
10 (CS/LD)SPI chip select / latch enableActive-low; initiates SPI frame on falling edge; latches gain setting on rising edge
11 (DIN)SPI serial data inputAccepts 8-bit gain code per channel (MSB first); synchronous with CLK
12 (CLK)SPI clock inputSupports up to 10 MHz clock rate; timing validated down to 30 ns setup/hold at 5 V

Key Features

FeatureDesign Value
Rail-to-rail I/O operationEnables full utilization of ADC input range in single-supply systems without level-shifting circuitry
Independent dual-channel SPI controlAllows asynchronous gain updates per channel - essential for dynamic ranging and chopper-stabilized architectures
Wired-OR output capabilityPermits analog multiplexing of OUTA/OUTB using external diodes or MOSFETs - reduces component count vs. discrete mux
Internal AGND reference generationEliminates need for external voltage divider or reference IC in single-supply designs - simplifies layout and BOM
Low power hardware shutdownReduces total supply current to ≤2 µA (GN-16 only); DFN-12 relies on software shutdown (≤255 µA/channel)

Applications

Data Acquisition SystemsAutomatic Gain Control Loops

Use Scenario: High-precision industrial sensor conditioning (e.g., strain gauge, RTD, thermocouple) feeding a 24-bit sigma-delta ADC.

IC Role / Device Role / Timing Role: Dual-channel PGA providing programmable gain scaling and offset compensation before ADC sampling.

Use Value: Achieves >115 dB system dynamic range by matching gain paths and minimizing noise contribution (12.6 nV/√Hz at G=100).

Use Scenario: RF receiver IF chain maintaining constant output amplitude despite varying input signal strength.

IC Role / Device Role / Timing Role: Inverting PGA adjusting gain in real time based on RSSI or envelope detector feedback.

Use Value: 0.1 dB channel matching ensures stable loop convergence; SPI interface allows microcontroller-driven closed-loop updates at <100 µs latency.

Dynamic Gain Changing CircuitsAutomatic Ranging Instruments

Use Scenario: Digital multimeter front-end switching between voltage ranges (e.g., 100 mV to 10 V full scale) without mechanical relays.

IC Role / Device Role / Timing Role: Dual PGA acting as programmable attenuator/amplifier pair for coarse/fine range selection.

Use Value: Eight discrete gain options (including G=0 attenuation) enable seamless range transitions with ≤2 mV offset error across temperature.

Use Scenario: Portable oscilloscope vertical amplifier auto-ranging across 1 mV/div to 10 V/div scales.

IC Role / Device Role / Timing Role: Primary signal-path PGA with independent channel control for dual-trace acquisition.

Use Value: Rail-to-rail I/O and 20 MHz gain-bandwidth product at G=10 support 100 kHz small-signal bandwidth even at highest gains.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel programmable gain amplifier applications.

Alternative PartTechnical DifferenceApplication DifferenceSelection Advice
LTC6912IDE-1#TRPBFSame pinout and functionality; specified for –40°C to 85°C industrial temperature grade (C-grade is commercial; I-grade is industrial)Required for extended ambient operation beyond 70°C; identical electrical specs except wider temp validationSelect when operating environment exceeds 70°C ambient or requires industrial qualification testing
AD8253ARMZSingle-channel, 32 V/V max gain, SPI interface, 10 nV/√Hz noise, but no G=0 or hardware shutdownLacks dual-channel independence and wired-OR capability; suited for single-path high-speed gain controlChoose when only one channel is needed and higher bandwidth (45 MHz GBW) outweighs dual-channel flexibility

Compared with LTC6912IDE-1#TRPBF and AD8253ARMZ, the LTC6912CDE-1#TRPBF offers unique dual-channel gain independence, G=0 attenuation mode, and DFN-12 thermal efficiency - making it optimal for space-constrained, multi-sensor data loggers requiring matched analog paths.

Availability

LTC6912CDE-1#TRPBF is available at Aetrix Electronics and suitable for data acquisition systems, automatic test equipment, and portable instrumentation requiring stable component supply, consistent parametric performance across production lots, and long-term lifecycle support.

Supply support for LTC6912CDE-1#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, formed through the acquisition of Linear Technology in 2017.

The LTC6912 family was designed specifically for precision, low-noise, digitally controlled analog signal conditioning - targeting applications where gain agility, channel matching, and DC accuracy are critical, such as medical instrumentation and scientific measurement.

FAQ

What gain settings does the LTC6912CDE-1#TRPBF support?

The LTC6912CDE-1#TRPBF supports eight discrete inverting voltage gains: 0, 1, 2, 5, 10, 20, 50, and 100 V/V. Gain is selected per channel via an 8-bit SPI register (Q3–Q0), with all settings verified across –40°C to 85°C. G=0 provides maximum attenuation (–120 dB), useful for input protection or blanking.

Does the LTC6912CDE-1#TRPBF support rail-to-rail input and output operation?

Yes, the LTC6912CDE-1#TRPBF supports rail-to-rail input voltage range and rail-to-rail output voltage swing under all supply conditions (2.7 V to 10.5 V total). At VS = 2.7 V, output swing is within 12 mV of each rail into 10 kΩ; at VS = 5 V, it is within 15–20 mV - enabling full dynamic range utilization with 3.3 V or 5 V ADCs.

Is hardware shutdown available on the LTC6912CDE-1#TRPBF?

No - hardware shutdown via the SHDN pin is only available on the GN-16 (SSOP) package variant (e.g., LTC6912CGN-1). The LTC6912CDE-1#TRPBF uses the 12-lead DFN package, which omits the SHDN pin. Power reduction is achieved via software shutdown (SPI state 1000), drawing ≤255 µA per channel at 2.7 V.

What is the purpose of the AGND pin on the LTC6912CDE-1#TRPBF?

The AGND pin on the LTC6912CDE-1#TRPBF provides an internally generated half-supply reference voltage (e.g., 2.5 V at VS = 5 V), essential for single-supply operation. It must be decoupled with a 1 µF capacitor to ensure stability and low-noise performance. This eliminates external reference components and simplifies biasing for AC-coupled sensor interfaces.

How does channel-to-channel isolation perform on the LTC6912CDE-1#TRPBF?

Channel-to-channel isolation on the LTC6912CDE-1#TRPBF is 113 dB at G = 1, 108 dB at G = 10, and 89 dB at G = 100 (f = 200 kHz, VS = 5 V). This high isolation is achieved through matched internal topology and requires proper PCB layout - including separate AGND/DGND planes and minimized inter-channel coupling - to maintain specified performance in sensitive multi-channel systems.

LTC6912CDE-1#TRPBF Specifications

Product attributes
Attribute value
Manufacturer:
Analog Devices Inc.
Series:
-
Package/Case:
12-WFDFN Exposed Pad
Packaging:
Tape & Reel (TR)
Product Status:
Active
Type:
Programmable Gain
Applications:
Data Acquisition
Mounting Type:
Surface Mount
Grade:
-
Qualification:
-
Supplier Device Package:
12-DFN (4x3)

LTC6912CDE-1#TRPBF FAQ

1.How can I place an order for LTC6912CDE-1#TRPBF through Aetrix?

Please submit a Request for Quotation (RFQ) for LTC6912CDE-1#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for LTC6912CDE-1#TRPBF reliable?

The price and inventory of LTC6912CDE-1#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC6912CDE-1#TRPBF is usually 5 days.

3.What payment methods are accepted for LTC6912CDE-1#TRPBF?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC6912CDE-1#TRPBF transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for LTC6912CDE-1#TRPBF?

LTC6912CDE-1#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your LTC6912CDE-1#TRPBF order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for LTC6912CDE-1#TRPBF?

For technical support, including LTC6912CDE-1#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC6912CDE-1#TRPBF requirements.

6.How does Aetrix verify that LTC6912CDE-1#TRPBF is sourced from the original manufacturer or authorized distributors?

All LTC6912CDE-1#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC6912CDE-1#TRPBF meets industry standards.

7.What is the process for return or replacement of LTC6912CDE-1#TRPBF?

All LTC6912CDE-1#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC6912CDE-1#TRPBF, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The LTC6912CDE-1#TRPBF part is unused and in its original packaging.

Return procedure for LTC6912CDE-1#TRPBF:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

LTC6912CDE-1#TRPBF Tags

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