Analog Devices Inc. LTC6915CGN#PBF
- Part No.:
- LTC6915CGN#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 16-SSOP (0.154", 3.90mm Width)
- Datasheet:
-
LTC6915CGN#PBF.pdf
- Description:
- IC INST AMP 1 CIRCUIT 16SSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,063
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Product details
Overview
LTC6915CGN#PBF from Analog Devices (formerly Linear Technology) is a zero-drift, precision instrumentation amplifier with digitally programmable gain of 0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, or 4096 via parallel or SPI interface. It delivers 125dB CMRR at any gain, <10µV max input offset voltage, and rail-to-rail input/output operation on single 2.7V–6V or dual ±5.5V supplies - used in high-resolution bridge sensor signal conditioning.
For engineers reviewing the LTC6915CGN#PBF datasheet, LTC6915CGN#PBF pinout, LTC6915CGN#PBF application, or LTC6915CGN#PBF equivalent, key selection criteria include guaranteed 0.1% typical gain accuracy across 14 gain levels, 50nV/°C max offset drift, 2.5µVP-P (0.01Hz–10Hz) input noise, and compatibility with both serial (SPI) and parallel gain control modes in the 16-lead SSOP package.
Technical Context
The LTC6915CGN#PBF employs charge-balanced sampled-data architecture: a 3kHz internal sampling switch transfers differential input voltage to a hold capacitor, translating common-mode level to the REF pin voltage before amplification by a zero-drift op amp. Gain is set by switching matched resistor arrays under digital control.
It supports two mutually exclusive interfaces: PARALLEL_SERIAL = V+ enables 4-bit parallel gain code (CS/D0, DIN/D1, CLK/D2, DOUT/D3), with HOLD_THRU latching; PARALLEL_SERIAL = V− enables SPI mode (CS active-low, MSB-first, DOUT synchronous output). Input aliasing is limited to signals <1.5kHz due to 3kHz sampling.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Programmable Gain Range | 0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096 - enables scalable signal amplification without hardware changes. |
| CMRR (Any Gain) | 125dB typical (LTC6915C, VS = 5V) - maintains high rejection of common-mode interference in noisy industrial environments. |
| Input Offset Voltage | ±10µV max (TA = –0°C to 70°C) - ensures minimal DC error in precision weigh scale and medical front-ends. |
| Offset Drift | ±50nV/°C max (–0°C to 70°C) - guarantees stable baseline over temperature in strain gauge and thermocouple applications. |
| Supply Range | 2.7V to ±5.5V - supports single-supply battery-powered systems and dual-supply high-dynamic-range acquisition. |
| Input Noise (0.01Hz–10Hz) | 2.5µVP-P - enables resolution of sub-microvolt signals in high-resolution data acquisition. |
| Internal Sampling Frequency | 3kHz - defines maximum usable input bandwidth (≤1.5kHz) and aliasing risk for anti-aliasing filter design. |
Pinout & Package
Package: 16-lead narrow plastic SSOP (GN), 0°C to 70°C operating temperature range, exposed pad not present.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 | SHDN | Hardware shutdown control: tie to V+ to disable (1µA supply current); floating pulls to V− internally. |
| 2 | IN− | Inverting analog input - accepts rail-to-rail common-mode voltage; differential input limited by VREF and supply rails. |
| 3 | IN+ | Noninverting analog input - matched to IN− for high CMRR; requires symmetric source impedances for optimal performance. |
| 4 | V− | Negative supply - also connects to exposed thermal pad in DFN variant; must be low-impedance for stability. |
| 5 | HOLD_THRU | Parallel mode latch enable: high holds current gain code; low or floating allows direct D0–D3 control (not present in DFN). |
| 6 | CS(D0) | Chip select (serial) / LSB gain bit (parallel) - active-low SPI enable; in parallel mode, sets gain bit 0 with 10k series resistor if driven >V+. |
| 7 | DIN(D1) | Serial data input (MSB-first) / gain bit 1 (parallel) - TTL-compatible; requires t1 ≥30ns setup before CLK rising edge (5V supply). |
| 8 | CLK(D2) | Serial clock input / gain bit 2 (parallel) - rising edge clocks DIN; falling edge outputs DOUT; min pulse width 50ns (5V). |
| 9 | PARALLEL_SERIAL | Interface mode select: V+ = parallel, V− = serial - hardwired logic; determines functional mapping of D0–D3 pins. |
| 10 | REF | Output reference voltage - sets DC level of OUT; must be within |VIN± − VREF| ≤ 5.5V to avoid damage. |
| 11 | OUT | Amplified single-ended output - rail-to-rail swing (e.g., 4.95V high / 17mV low @ 200µA, VS = 5V); load ≥1kΩ for <0.1% gain error. |
| 12 | V+ | Positive supply - bypass with 0.1µF ceramic capacitor near pin; max total supply voltage = 11V (V+ to V−). |
| 13 | SENSE | Remote sense for load compensation - connect directly to load to correct for trace resistance errors in low-R drive scenarios. |
| 14 | NC | No connect - no internal connection; leave unconnected or grounded per layout best practice. |
| 15 | DGND | Digital ground - separate from analog ground in mixed-signal layouts; ties to internal digital circuitry and I/O buffers. |
| 16 | DOUT(D3) | Serial data output (active, not tri-stated) / MSB gain bit (parallel) - bidirectional in parallel mode; limit current to ≤5mA if driven >V+. |
Key Features
| Feature | Design Value |
|---|---|
| Zero-drift architecture | Eliminates 1/f noise and minimizes long-term drift - critical for DC-coupled sensor interfaces requiring <1µV/h stability. |
| Rail-to-rail input/output | Maximizes dynamic range on low-voltage supplies (e.g., 2.7V) - captures full sensor output swing without level-shifting. |
| 14 discrete gain levels | Enables precise scaling of microvolt-level bridge outputs to ADC full-scale - avoids external gain-switching relays or op-amp networks. |
| 125dB CMRR independent of gain | Maintains immunity to power supply ripple and EMI regardless of selected gain - essential for high-gain thermocouple amplifiers. |
| Parallel + SPI interface support | Allows flexible system integration: parallel for simple microcontroller GPIO use; SPI for daisy-chained multi-channel configurations. |
| Shutdown mode (1–4µA) | Reduces power in idle periods - extends battery life in portable medical devices and IoT sensor nodes with intermittent sampling. |
Applications
| Thermocouple Amplifier | Electronic Scale |
|---|---|
|
Use Scenario: Amplifying µV-level Seebeck voltage from K-type thermocouples across –200°C to +1372°C with cold-junction compensation. IC Role / Device Role / Timing Role: Precision instrumentation amplifier with programmable gain (e.g., 128× or 512×) and REF pin referenced to cold-junction sensor. Use Value: ±10µV offset and ±50nV/°C drift ensure <0.5°C measurement accuracy without frequent recalibration. |
Use Scenario: Conditioning mV-output Wheatstone bridge signals from load cells in commercial weighing platforms (0.1g–100kg range). IC Role / Device Role / Timing Role: Differential-to-single-ended converter with selectable gain (e.g., 1024×) and rail-to-rail output driving 24-bit sigma-delta ADC. Use Value: 125dB CMRR rejects common-mode noise from AC mains and motor drives; 2.5µVP-P noise enables 1:1,000,000 resolution. |
| Medical Instrumentation | Strain Gauge Amplifier |
|
Use Scenario: Front-end amplification of biopotential signals (ECG, EEG) with adjustable gain to accommodate varying electrode contact impedances. IC Role / Device Role / Timing Role: Low-noise, high-CMRR PGA providing gain from 1× to 1024× via SPI-controlled configuration during device boot-up. Use Value: Zero-drift architecture prevents baseline wander; 2.7V minimum supply enables operation from coin-cell batteries in portable monitors. |
Use Scenario: Signal conditioning for bonded foil strain gauges in structural health monitoring (e.g., bridge deformation sensors). IC Role / Device Role / Timing Role: High-precision bridge amplifier with SENSE pin compensation for long cable runs between sensor and PCB. Use Value: SENSE pin feedback reduces gain error from interconnect resistance; 0.1% gain accuracy ensures calibrated force measurement traceability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar instrumentation amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD8253ARMZ | Fixed 4 gain options (1, 10, 100, 1000); SPI-only interface; 10µV max offset; 100dB CMRR at G=100. | Limited to coarse gain steps; lacks zero-drift architecture - higher drift (0.3µV/°C) limits DC stability. | Choose AD8253ARMZ when only four standardized gains are needed and lower cost is prioritized over ultra-low drift. |
| INA333AIDRGT | Fixed G=1, 5, 10, 100; no digital interface; 25µV max offset; 100dB CMRR; 0.15µV/°C drift. | Analog-only gain setting via external resistor; no programmability; higher offset and drift than LTC6915CGN#PBF. | Choose INA333AIDRGT for simple, low-pin-count designs where gain is fixed per board revision and lowest BOM count matters. |
Compared with AD8253ARMZ and INA333AIDRGT, the LTC6915CGN#PBF provides 14 discrete, software-selectable gains with superior DC precision (±10µV offset, ±50nV/°C drift) and higher CMRR (125dB), making it optimal for applications demanding both flexibility and metrology-grade accuracy.
Availability
LTC6915CGN#PBF is available at Aetrix Electronics and suitable for electronic scales, medical instrumentation, thermocouple amplifiers, and strain gauge signal conditioning requiring stable component supply across industrial and medical OEM programs.
Supply support for LTC6915CGN#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors.
The LTC6915CGN#PBF belongs to Linear's precision instrumentation amplifier product line, designed specifically for high-accuracy, low-drift sensor signal conditioning in test equipment, industrial automation, and medical diagnostics.
FAQ
What is the maximum input signal frequency supported by the LTC6915CGN#PBF?
The LTC6915CGN#PBF uses a 3kHz internal sampling clock, resulting in a Nyquist limit of 1.5kHz. Input signals above this frequency will alias into the baseband. For accurate amplification, bandlimit the input using an external anti-aliasing filter with cutoff ≤1.5kHz. This applies regardless of gain setting or supply voltage.
Can the LTC6915CGN#PBF operate with a single 3.3V supply?
Yes, the LTC6915CGN#PBF operates from 2.7V to 6V single supply or ±5.5V dual supply. At V+ = 3.3V and V− = 0V, it maintains rail-to-rail input/output swing, 125dB CMRR, and ±10µV max offset. Ensure VREF is set within safe margins (e.g., 1.65V) and |VIN± − VREF| ≤ 5.5V - which is inherently satisfied at 3.3V.
How does the HOLD_THRU pin function in the LTC6915CGN#PBF?
HOLD_THRU (Pin 5) is active-high and exclusive to the GN (SSOP) package. When high, it latches the parallel gain code (D3–D0) into an internal 4-bit register, freezing gain despite changes on D0–D3. When low or floating, gain updates immediately with D0–D3. The DFN package omits this pin - its parallel mode is always transparent.
What is the purpose of the SENSE pin on the LTC6915CGN#PBF?
The SENSE pin (Pin 13) enables Kelvin sensing for improved gain accuracy when driving low-impedance loads. Connect SENSE directly to the load terminal instead of the OUT pin to compensate for voltage drop across PCB traces or cables. This reduces gain error caused by interconnect resistance, especially critical in precision weighing systems.
Is the LTC6915CGN#PBF pin-compatible with other packages in the LTC6915 family?
No - the LTC6915CGN#PBF (16-lead SSOP) is not pin-compatible with the LTC6915CDE#PBF (12-lead DFN). Key differences include presence of SHDN and HOLD_THRU pins in GN but not DFN, and different pin numbering/assignments for DOUT, DGND, and SENSE. Board layout must be specific to the chosen package.
LTC6915CGN#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-SSOP (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- Instrumentation
- Number of Circuits:
- 1
- Output Type:
- Rail-to-Rail
- Slew Rate:
- 0.2V/µs
- Gain Bandwidth Product:
- 200 kHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 4 nA
- Voltage - Input Offset:
- 5 µV
- Current - Supply:
- 1.73mA
- Current - Output / Channel:
- -
- Voltage - Supply Span (Min):
- 2.7 V
- Voltage - Supply Span (Max):
- 11 V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SSOP
LTC6915CGN#PBF FAQ
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For technical support, including LTC6915CGN#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC6915CGN#PBF requirements.
6.How does Aetrix verify that LTC6915CGN#PBF is sourced from the original manufacturer or authorized distributors?
All LTC6915CGN#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC6915CGN#PBF meets industry standards.
7.What is the process for return or replacement of LTC6915CGN#PBF?
All LTC6915CGN#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC6915CGN#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC6915CGN#PBF part is unused and in its original packaging.
Return procedure for LTC6915CGN#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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