Analog Devices Inc. LTC6915IDE#PBF
- Part No.:
- LTC6915IDE#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 12-WFDFN Exposed Pad
- Datasheet:
-
LTC6915IDE#PBF.pdf
- Description:
- IC INST AMP 1 CIRCUIT 12DFN
- Quantity:
- Payment:

- Shipping:

Inventory:300
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Product details
Overview
LTC6915IDE#PBF from Analog Devices (formerly Linear Technology) is a zero-drift, precision instrumentation amplifier with digitally programmable gain up to 4096 via SPI or parallel interface. It delivers 125dB CMRR at any gain, <10µV offset, and rail-to-rail input/output operation on single 2.7V–6V or dual ±5.5V supplies - ideal for high-resolution bridge sensor conditioning in industrial weighing systems.
For engineers reviewing the LTC6915IDE#PBF datasheet, LTC6915IDE#PBF pinout, LTC6915IDE#PBF application, or LTC6915IDE#PBF equivalent, key selection criteria include guaranteed 50nV/°C max offset drift over –40°C to 85°C, 14 discrete gain levels (0–4096), SPI timing compliance at 4MHz, and DFN-12 package thermal performance (θJA = 160°C/W).
Technical Context
The LTC6915IDE#PBF employs charge-balanced sampled-data architecture with 3kHz internal sampling frequency, converting differential inputs to single-ended signals before amplification by a zero-drift op amp. Gain is set by switching matched resistor arrays, enabling 14 precise gain states without external components.
It supports two digital control modes: serial (SPI-compatible, 4-wire, MSB-first) and parallel (4-bit latch with HOLD_THRU). The DFN-12 variant internally ties HOLD_THRU to DGND, simplifying layout versus the SSOP-16 version which exposes this pin.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Gain Range | 0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096 - discrete, factory-trimmed steps; no interpolation required |
| CMRR | 125dB typical at AV=1024, VCM=0.1V–4.9V (LTC6915I grade); independent of gain setting |
| Input Offset Voltage | ±10µV max over –40°C to 85°C; enables sub-16-bit accuracy in DC-coupled strain gauge interfaces |
| Offset Drift | ±50nV/°C max over –40°C to 85°C; ensures stable baseline in temperature-varying medical sensors |
| Supply Range | 2.7V to ±5.5V; supports battery-powered portable instrumentation and industrial 5V/±5V rails |
| Output Swing | Rail-to-rail: 4.95V high / 17mV low (sinking 200µA, V+=5V, V−=0V); minimizes headroom loss in low-voltage ADC front ends |
| Interface Timing | t8 = 85ns DOUT delay (CL=15pF, V+=4.5–5.5V); ensures reliable SPI communication at 4MHz clock |
Pinout & Package
Package: 12-lead (4mm × 3mm) plastic DFN with exposed V− pad (Pin 13), θJA = 160°C/W. Must be soldered to PCB for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN– (Pin 1) | Inverting analog input | Accepts rail-to-rail common-mode voltage; differential input range limited by VREF and supply rails |
| IN+ (Pin 2) | Noninverting analog input | Paired with IN– for true differential sensing; matched input bias current (5–10nA) minimizes RS mismatch error |
| V– (Pin 3) | Negative supply / Exposed thermal pad | Internally connected to exposed pad; must be soldered to PCB ground plane for thermal dissipation and noise immunity |
| CS(D0) (Pin 4) | SPI chip select / Parallel LSB | Active-low SPI enable; in parallel mode, defines gain bit D0 (LSB) - requires external pull-up if unused |
| DIN(D1) (Pin 5) | SPI data input / Parallel D1 | Serial data input (MSB-first); in parallel mode, sets gain bit D1 - TTL-compatible, 0.8V/2.0V thresholds |
| CLK(D2) (Pin 6) | SPI clock / Parallel D2 | Drives internal shift register on rising edge; in parallel mode, sets gain bit D2 - max 4MHz operation |
| DOUT(D3) (Pin 7) | SPI data output / Parallel D3 (MSB) | Bidirectional: outputs serial data on falling edge; in parallel mode, accepts D3 input - clamp resistor required if driven >V+ |
| DGND (Pin 8) | Digital ground reference | Separate from analog ground; decoupling capacitor required between DGND and V– for SPI noise suppression |
| PARALLEL_SERIAL (Pin 9) | Interface mode select | Tie to V+ for parallel control; tie to V– for SPI - determines whether D0–D3 function as data or control lines |
| REF (Pin 10) | Output reference voltage | Sets output common-mode level; drives external DAC reference or ADC input; 0V to V+–1.3V range |
| OUT (Pin 11) | Amplified single-ended output | Capable of sourcing/sinking 2mA; load resistance ≥1kΩ recommended for <0.1% gain error |
| V+ (Pin 12) | Positive supply | Accepts 2.7–6V single or +5.5V in dual-supply; bypass capacitor mandatory at pin for PSRR stability |
Key Features
| Feature | Design Value |
|---|---|
| Zero-drift architecture | Eliminates 1/f noise and thermal hysteresis; enables stable DC measurements over time and temperature |
| 14-step programmable gain | Factory-trimmed resistor array ensures ±0.6% max gain error at AV=64–1024; no calibration needed per channel |
| Rail-to-rail I/O | Full dynamic range utilization on 3V supplies; eliminates level-shifting circuitry in low-power sensor nodes |
| Internal 3kHz sampling | Fixed-frequency switched-capacitor front end; aliasing controlled by external anti-alias filter below 1.5kHz |
| Hardware/software shutdown | Reduces quiescent current to 4µA (software) or 1µA (hardware); enables µA-level sleep modes in portable devices |
Applications
| Thermocouple Amplifier | Electronic Scale Load Cell Interface |
|---|---|
Use Scenario: Cold-junction compensation and microvolt-level thermocouple signal amplification in HVAC controllers. IC Role / Device Role / Timing Role: Precision differential amplifier with programmable gain (AV=128–512) and REF pin referenced to cold-junction sensor. Use Value: ±10µV offset and ±50nV/°C drift ensure <0.5°C measurement accuracy across –40°C to 85°C ambient. |
Use Scenario: Strain gauge bridge output amplification in platform scales with 20,000-count resolution. IC Role / Device Role / Timing Role: Bridge excitation buffer and PGA front end; gain dynamically adjusted to match full-scale weight range. Use Value: 125dB CMRR rejects common-mode noise from AC mains and motor drives in factory environments. |
| Medical ECG Front End | High-Resolution Data Acquisition |
Use Scenario: Low-noise biopotential amplification in portable ECG monitors with lead-off detection. IC Role / Device Role / Timing Role: First-stage instrumentation amplifier; gain set to AV=100 for 1mV p-p ECG signals, REF biased at 1.25V. Use Value: 2.5µVP-P (0.01Hz–10Hz) input noise preserves QRS complex fidelity without oversampling. |
Use Scenario: Multi-channel sensor hub in test equipment requiring simultaneous high-precision DC measurements. IC Role / Device Role / Timing Role: Channel-multiplexed PGA with SPI daisy-chaining; 14 gain states accommodate diverse sensor sensitivities. Use Value: Serial interface allows single MCU GPIO to configure up to 8 LTC6915IDE#PBF devices, reducing BOM count and routing complexity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar instrumentation amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD8420ARMZ | Fixed gain (10–1000), no digital programming; 120dB CMRR, 50nV/°C drift, SOIC-8 | Requires external gain-setting resistors; lacks SPI/parallel interface for dynamic range adaptation | Select when gain is static and board space is constrained; not suitable for auto-ranging architectures |
| INA333AIDRGT | Zero-drift, 1–1000 gain via RG; 100dB CMRR, 25nV/°C drift, VSSOP-8 | Analog gain adjustment only; no digital control; lower supply current (50µA) but no shutdown mode | Prefer for ultra-low-power battery operation where gain remains fixed per channel |
Compared with AD8420ARMZ and INA333AIDRGT, the LTC6915IDE#PBF uniquely combines programmable gain, rail-to-rail I/O, and hardware shutdown in a thermally optimized DFN-12 package - essential for adaptive sensor systems requiring field-upgradable gain profiles and thermal management.
Availability
LTC6915IDE#PBF is available at Aetrix Electronics and suitable for industrial weighing systems, medical diagnostic equipment, and high-accuracy data acquisition requiring stable component supply across extended temperature ranges.
Supply support for LTC6915IDE#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, acquired Linear Technology in 2017.
The LTC6915IDE#PBF belongs to ADI's precision instrumentation amplifier product line, engineered for DC-critical applications demanding ultra-low offset, near-zero drift, and programmable gain without external components.
FAQ
What is the operating temperature range for the LTC6915IDE#PBF?
The LTC6915IDE#PBF is rated for –40°C to +85°C ambient operation, matching the "I" grade specification. This range is validated across all electrical parameters including ±10µV max input offset voltage and ±50nV/°C max offset drift, making it suitable for industrial and automotive cabin environments where thermal stability is critical.
Does the LTC6915IDE#PBF support both SPI and parallel gain control simultaneously?
No - the LTC6915IDE#PBF uses the PARALLEL_SERIAL pin (Pin 9) to select one interface mode exclusively. When tied to V+, it operates in parallel mode using D0–D3 as gain bits; when tied to V–, it enters SPI mode with CS/DIN/CLK/DOUT active. Mixing modes is not supported and may cause undefined behavior.
How does the DFN-12 package of the LTC6915IDE#PBF differ from the SSOP-16 version in functionality?
The LTC6915IDE#PBF (DFN-12) omits the HOLD_THRU and SENSE pins present in the SSOP-16 variant. HOLD_THRU is internally tied to DGND, fixing parallel-mode latching behavior. SENSE is absent, meaning remote sensing for load regulation is unavailable - output accuracy relies on direct OUT pin connection to the load.
What is the maximum clock frequency supported for SPI communication with the LTC6915IDE#PBF?
The LTC6915IDE#PBF supports continuous SPI clock frequencies up to 4MHz under V+ = 4.5–5.5V conditions, with t8 = 85ns DOUT propagation delay (CL = 15pF). At lower supplies (2.7–4.5V), max clock drops to 2MHz; timing margins must be verified per actual V+ and capacitive loading.
Can the LTC6915IDE#PBF be used with dual ±5V supplies, and what are the input voltage limits?
Yes - the LTC6915IDE#PBF operates with dual ±5V supplies. Input pins (IN+, IN–) must remain within V– to V+ rails, and |VIN+ – VREF| and |VIN– – VREF| must each stay ≤5.5V. For ±5V operation, VREF should be set to 0V or ±0.5V to maintain rail-to-rail input common-mode range without exceeding absolute maximum ratings.
LTC6915IDE#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 12-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- Instrumentation
- Number of Circuits:
- 1
- Output Type:
- Rail-to-Rail
- Slew Rate:
- 0.2V/µs
- Gain Bandwidth Product:
- 200 kHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 4 nA
- Voltage - Input Offset:
- 5 µV
- Current - Supply:
- 1.73mA
- Current - Output / Channel:
- -
- Voltage - Supply Span (Min):
- 2.7 V
- Voltage - Supply Span (Max):
- 11 V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 12-DFN (4x3)
LTC6915IDE#PBF FAQ
1.How can I place an order for LTC6915IDE#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC6915IDE#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC6915IDE#PBF reliable?
The price and inventory of LTC6915IDE#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC6915IDE#PBF is usually 5 days.
3.What payment methods are accepted for LTC6915IDE#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC6915IDE#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC6915IDE#PBF?
LTC6915IDE#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC6915IDE#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC6915IDE#PBF?
For technical support, including LTC6915IDE#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC6915IDE#PBF requirements.
6.How does Aetrix verify that LTC6915IDE#PBF is sourced from the original manufacturer or authorized distributors?
All LTC6915IDE#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC6915IDE#PBF meets industry standards.
7.What is the process for return or replacement of LTC6915IDE#PBF?
All LTC6915IDE#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC6915IDE#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC6915IDE#PBF part is unused and in its original packaging.
Return procedure for LTC6915IDE#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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