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Analog Devices Inc. LTC691CN#PBF
- Part No.:
- LTC691CN#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
LTC691CN#PBF.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 16DIP
- Quantity:
- Payment:
- Shipping:
Inventory:189
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Product details
Overview
LTC691CN#PBF from Analog Devices (formerly Linear Technology) is a 16-pin microprocessor supervisory IC with integrated battery backup switching, power-fail warning, watchdog timer, and RAM write-protection gating. It features a 4.65V precision reset threshold, guaranteed RESET assertion down to VCC = 1V, 50ms typical reset active time (adjustable), and supports up to 50mA VOUT supply current from VCC or VBATT. It is used in battery-backed microcontroller systems requiring reliable power monitoring and memory integrity during brownouts.
For engineers reviewing the LTC691CN#PBF datasheet, LTC691CN#PBF pinout, LTC691CN#PBF application, or LTC691CN#PBF equivalent, key selection criteria include its dual reset outputs (RESET/RESET), CE IN/CE OUT memory protection logic, adjustable reset timing via OSC SEL/OSC IN, and 16-lead PDIP package with 0°C to 70°C operating range.
Technical Context
The LTC691CN#PBF integrates five core functional blocks: (1) a precision 4.65V voltage monitor with 40mV hysteresis and guaranteed operation down to VCC = 1V; (2) a charge-pumped NMOS VOUT switch (5Ω typical RDS(on)) delivering up to 50mA from VCC, plus a 125Ω PMOS battery switchover switch; (3) a dual-mode watchdog timer with internal oscillator (100ms/1.6s timeout) or external clock input; (4) a power-fail comparator (1.3V reference, ±25nA input bias); and (5) a chip-enable gating circuit with 20ns propagation delay and forced-high CE OUT during undervoltage.
Its 16-pin PDIP package hosts dedicated pins for battery control (VBATT, BATT ON), memory protection (CE IN, CE OUT), and system signaling (PFI/PFO, WDI/WDO, LOWLINE), enabling full µP supervision without external components beyond bypass capacitors and optional pull-ups.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reset Threshold | 4.65V typical (4.5–4.75V min/max); ensures reliable µP reset before 5V rail collapse |
| Reset Active Time | 50ms typical (35–70ms min/max); adjustable via OSC SEL/OSC IN for custom power-up stabilization |
| VOUT Output Capability | 50mA max from VCC (5Ω RDS(on)); powers CMOS RAM directly without external regulators |
| Battery Switchover | Triggers at VCC – VBATT = 70mV (power-up) / 50mV (power-down); 20mV hysteresis prevents chatter |
| Supply Current | 1.5mA max (active), 1µA max (battery-backup mode); enables long-term RAM retention on coin cell |
| Watchdog Timeout | 100ms / 1.6s selectable (internal OSC); detects firmware hangs without external timing components |
| Operating Temp Range | 0°C to 70°C; validated for commercial embedded systems and industrial controllers |
Pinout & Package
Package: 16-lead plastic DIP (N package), 0°C to 70°C operating range, through-hole mounting.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | 5V main supply input | Bypassed with 0.1µF capacitor; powers all internal circuits and VOUT NMOS switch |
| VOUT | Backed-up memory supply output | Delivers up to 50mA from VCC or VBATT; connects to CMOS RAM VCC pin |
| VBATT | Battery backup input | Accepts 2.0–4.25V; enables VOUT sourcing from auxiliary power when VCC fails |
| GND | Ground reference | Common return for all analog/digital functions; requires low-impedance PCB connection |
| BATT ON | Battery status logic output | Sinks 35mA; drives external PNP transistor base to boost VOUT current beyond 50mA |
| OSC IN | Oscillator input | Accepts external clock or capacitor (47pF) to adjust reset/watchdog timing; floating disables oscillator |
| LOWLINE | VCC undervoltage indicator | Active-low output mirroring RESET threshold crossing; used for system-level fault signaling |
| OSC SEL | Oscillator mode select | High/floating = internal OSC; low = external clock/capacitor mode for timing flexibility |
| WDO | Watchdog timeout flag | Active-low output asserting when WDI is un-toggled beyond timeout; resets µP via RESET |
| CE IN | Chip enable input | Accepts µP address decoder signal; gates CE OUT to prevent RAM writes during undervoltage |
| CE OUT | Protected chip enable output | Buffered CE IN replica during normal operation; forced high during reset to lock RAM writes |
| WDI | Watchdog input | Three-level input (high/low/floating); transitions reset watchdog timer; floating disables function |
| PFO | Power-fail warning output | Active-low comparator output triggered when PFI < 1.3V; interrupts µP for controlled shutdown |
| PFI | Power-fail input | Non-inverting comparator input; connected to voltage divider sensing primary supply decay |
| RESET | Active-low reset output | Guaranteed low down to VCC = 1V; holds µP in reset until stable 5V is confirmed |
| RESET | Active-high reset output | Inverse of RESET; provides logic-high reset signal for µPs requiring active-high assertion |
Key Features
| Feature | Design Value |
|---|---|
| Dual reset outputs (RESET/RESET) | Provides both active-low and active-high reset signals to match any µP interface requirement |
| Adjustable reset timing | OSC SEL/OSC IN pins allow user-defined reset pulse width (35–280ms) without external RC networks |
| Integrated RAM write protection | CE IN/CE OUT gating forces CE high during undervoltage, preventing corrupt writes to battery-backed RAM |
| Low-dropout battery switchover | Charge-pumped NMOS (5Ω) + PMOS (125Ω) switches enable <100mV dropout and 1µA standby current |
| Early power-fail warning | PFI/PFO comparator with 1.3V reference and sub-µs response enables 8+ ms shutdown window before RESET asserts |
| Thermal-safe operation | Short-circuit protected VOUT and thermal shutdown (~155°C) prevent damage during overload or miswiring |
Applications
| Industrial PLC Controller | Medical Data Logger |
|---|---|
Use Scenario: Maintains real-time clock and sensor calibration data during AC mains interruption or brownout. IC Role / Device Role / Timing Role: Supervises 5V system rail, backs up SRAM via VOUT/VBATT, asserts RESET to halt CPU, and triggers PFO interrupt for graceful data save. Use Value: Guarantees data integrity across >10,000 power cycles with no external backup controller or discrete MOSFETs. |
Use Scenario: Preserves patient vital sign history in portable ECG monitor during battery swap or low-battery condition. IC Role / Device Role / Timing Role: Monitors main Li-ion supply (VBATT), gates EEPROM write access via CE OUT, and asserts RESET if VCC drops below 4.65V during critical acquisition. Use Value: Eliminates need for external supervisor + backup switch IC, reducing BOM count by 2 parts and PCB area by 35%. |
| Automotive Infotainment Head Unit | Smart Energy Meter |
Use Scenario: Prevents firmware corruption during vehicle ignition cycling or alternator voltage sag. IC Role / Device Role / Timing Role: Uses WDI to verify bootloader execution, triggers watchdog reset on hang, and forces CE OUT high to lock flash programming during undervoltage. Use Value: Achieves ASIL-B compatible reset behavior with 35ms minimum pulse width and 1V fail-safe operation. |
Use Scenario: Secures metering registers and tariff tables during grid outage or tamper-induced power cut. IC Role / Device Role / Timing Role: Detects AC loss via PFI voltage divider, initiates PFO interrupt for secure storage, then asserts RESET after 50ms to freeze counters. Use Value: Meets IEC 62053-21 requirements for tamper-resilient data retention with <1µA battery drain. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX691ACPP+ | 8-pin SOIC, fixed 200ms reset time, no CE IN/CE OUT, no adjustable timing | Lacks RAM write protection gating and timing flexibility; suitable only for basic reset-only use cases | Select when board space is constrained and memory protection is handled externally |
| TPS3823MPW | 8-pin TSSOP, 3.08V reset threshold, no battery backup, no watchdog, no PFI/PFO | Provides only voltage monitoring and reset; cannot support battery-backed RAM or early power-fail warning | Select for cost-sensitive 3.3V systems where backup and warning functions are unnecessary |
Compared with MAX691ACPP+ and TPS3823MPW, the LTC691CN#PBF delivers unique integration of battery switchover, dual reset outputs, CE gating, and adjustable timing - enabling single-chip supervision for complex µP systems where data integrity and fail-safe operation are mandatory.
Availability
LTC691CN#PBF is available at Aetrix Electronics and suitable for industrial PLC controllers, medical data loggers, automotive infotainment head units, smart energy meters, and battery-powered instrumentation requiring stable component supply and long-term lifecycle support.
Supply support for LTC691CN#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTC691CN#PBF belongs to the LTC690 family of microprocessor supervisory ICs, designed specifically to consolidate power monitoring, battery backup, memory protection, and watchdog functionality into a single IC for embedded systems demanding robustness and minimal external components.
FAQ
What is the guaranteed minimum VCC level at which LTC691CN#PBF asserts RESET?
The LTC691CN#PBF guarantees RESET remains logic low even when VCC drops as low as 1V, ensuring the microprocessor stays in a known reset state during deep brownouts. This specification is verified over temperature and applies regardless of VBATT voltage. The LTC691CN#PBF achieves this via an internal low-voltage detection circuit independent of the main 4.65V threshold comparator, making it suitable for systems where residual rail energy must be fully exhausted before release.
How does the CE IN/CE OUT function protect CMOS RAM in LTC691CN#PBF?
The LTC691CN#PBF uses CE IN as a buffered input from the microprocessor's address decoder, and CE OUT as a gated output driving the RAM's chip-enable pin. When VCC is above 4.65V, CE OUT replicates CE IN with 20ns delay; when VCC falls below threshold, CE OUT is forced high-preventing write operations to battery-backed RAM. This ensures data integrity during power transitions. The LTC691CN#PBF implements this entirely internally, eliminating need for external logic or pull-up resistors.
Can LTC691CN#PBF support adjustable reset timing, and how is it configured?
Yes, the LTC691CN#PBF supports adjustable reset timing via OSC SEL and OSC IN pins. With OSC SEL high or floating, the internal oscillator sets a fixed 50ms typical reset pulse. Pulling OSC SEL low enables external timing: applying a clock signal to OSC IN or connecting a capacitor (e.g., 47pF) between OSC IN and GND allows precise adjustment of reset duration from 35ms to 280ms. This configurability is documented in the LTC691CN#PBF Applications Information section and eliminates trimming resistors or capacitors on the PCB.
What is the maximum continuous current LTC691CN#PBF can deliver from VOUT in battery-backup mode?
In battery-backup mode (VCC < VBATT), the LTC691CN#PBF delivers VOUT from VBATT through a 125Ω PMOS switch, supporting up to 250µA continuous output current while maintaining regulation. This is sufficient for low-power CMOS RAM and real-time clocks. For higher currents, the LTC691CN#PBF relies on its BATT ON output to drive an external PNP transistor, extending capability beyond 50mA. The 1µA max standby current ensures multi-year coin-cell life.
Does LTC691CN#PBF provide both power-fail warning and reset assertion, and how are they related?
Yes, the LTC691CN#PBF provides independent power-fail warning (PFO) and reset assertion (RESET). PFO activates when PFI voltage falls below 1.3V-typically set via external resistor divider to trigger 8–15ms before RESET asserts at 4.65V. This gives the microprocessor time to execute shutdown routines. RESET remains inactive until VCC crosses the 4.65V threshold, ensuring deterministic sequencing. Both functions operate simultaneously and are electrically isolated within the LTC691CN#PBF block diagram.
LTC691CN#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 4.65V
- Output:
- Open Drain or Open Collector
- Reset:
- Active High/Active Low
- Reset Timeout:
- 35ms Minimum
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-PDIP
LTC691CN#PBF FAQ
1.How can I place an order for LTC691CN#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC691CN#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC691CN#PBF reliable?
The price and inventory of LTC691CN#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC691CN#PBF is usually 5 days.
3.What payment methods are accepted for LTC691CN#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC691CN#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC691CN#PBF?
LTC691CN#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC691CN#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC691CN#PBF?
For technical support, including LTC691CN#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC691CN#PBF requirements.
6.How does Aetrix verify that LTC691CN#PBF is sourced from the original manufacturer or authorized distributors?
All LTC691CN#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC691CN#PBF meets industry standards.
7.What is the process for return or replacement of LTC691CN#PBF?
All LTC691CN#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC691CN#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC691CN#PBF part is unused and in its original packaging.
Return procedure for LTC691CN#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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