Analog Devices Inc. LTC691CSW#TRPBF

Overview

LTC691CSW#TRPBF from Analog Devices (formerly Linear Technology) is a 16-pin microprocessor supervisory IC with integrated battery backup switching, power-fail warning, watchdog timer, and RAM write-protection gating. It features a 4.65V precision reset threshold, guaranteed RESET assertion down to VCC = 1V, 35ns CE OUT propagation delay, and dual active-low/high RESET outputs. It is used in battery-backed CMOS RAM systems requiring reliable power monitoring and memory integrity during brownout or main supply loss.

For engineers reviewing the LTC691CSW#TRPBF datasheet, LTC691CSW#TRPBF pinout, LTC691CSW#TRPBF application, or LTC691CSW#TRPBF equivalent, key selection criteria include guaranteed sub-1.5V reset hold, adjustable reset timeout (via OSC SEL/OSC IN), 50mA VOUT supply capability, and conditional battery switchover with 70mV power-up/50mV power-down thresholds - all critical for industrial controllers and automotive ECUs with volatile memory retention requirements.

Technical Context

The LTC691CSW#TRPBF implements a bandgap-referenced voltage comparator (C1) for precise 4.65V ±150mV reset detection with 40mV hysteresis, ensuring immunity to VCC transients. Its charge-pumped NMOS VOUT switch delivers up to 50mA at <5Ω on-resistance, while a separate PMOS battery switch enables low-dropout VBATT-to-VOUT transfer with 125Ω typical resistance and 1µA standby current.

It integrates a dual-mode watchdog timer (internal oscillator or external clock input), a programmable power-fail comparator (1.3V reference, 1.25–1.35V PFI threshold), and a buffered CE IN/CE OUT gating path with 20ns propagation delay and logic-level translation - enabling direct interface to CMOS RAM chip-enable inputs during both normal and battery-backup operation.

Key Specifications

Pinout & Package

Package: 16-lead wide plastic SO (SW), 0°C to 70°C operating range, JEDEC MS-013AC compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with MAX691ACSE+ and TPS3823-50DBVR, the LTC691CSW#TRPBF uniquely integrates battery-backed VOUT delivery, dual-reset outputs, CE gating, and programmable timing - making it the only option among the three that fully satisfies concurrent requirements for memory integrity, power-fail warning, and supervised switchover in industrial and automotive systems.

Availability

LTC691CSW#TRPBF is available at Aetrix Electronics and suitable for industrial PLC memory backup, automotive body control modules, and medical infusion pump controllers requiring stable component supply and long-term lifecycle support.

Supply support for LTC691CSW#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors for precision instrumentation, power management, and reliability-critical systems.

The LTC691CSW#TRPBF belongs to the LTC690 family of microprocessor supervisory ICs, designed specifically to consolidate reset generation, battery backup control, power-fail warning, and RAM write protection into a single package for mission-critical embedded computing.

FAQ

What is the minimum VCC voltage at which LTC691CSW#TRPBF guarantees RESET remains asserted?

LTC691CSW#TRPBF guarantees the RESET output stays logic low down to VCC = 1V, ensuring the microprocessor remains in a defined reset state even during deep brownout conditions or capacitor discharge decay. This specification is verified across temperature and load, and enables robust fail-safe behavior in systems with extended hold-up time requirements. The LTC691CSW#TRPBF achieves this via dedicated low-voltage bias circuitry independent of the main comparator supply path.

How does LTC691CSW#TRPBF handle battery switchover between VCC and VBATT?

LTC691CSW#TRPBF uses a comparator (C2) with 70mV power-up and 50mV power-down thresholds and 20mV hysteresis to switch VOUT between VCC and VBATT. When VCC rises above VBATT + 70mV, VOUT connects to VCC through an NMOS switch; when VCC falls below VBATT + 50mV, VOUT connects to VBATT through a PMOS switch. This prevents oscillation and minimizes battery drain. The LTC691CSW#TRPBF implements this entirely in hardware with no software dependency.

Can LTC691CSW#TRPBF be used to protect nonvolatile RAM without external components?

Yes - LTC691CSW#TRPBF provides direct hardware write protection via its CE IN/CE OUT interface. When VCC drops below 4.65V, CE OUT is forced high regardless of CE IN state, disabling RAM write access within 20ns. This eliminates the need for external logic or pull-up resistors in standard CMOS RAM applications. The LTC691CSW#TRPBF's CE OUT output is rail-to-rail compatible and rated for 3.2mA sink current, supporting direct connection to common RAM CE/WE pins.

What is the function of the BATT ON pin on LTC691CSW#TRPBF?

The BATT ON pin on LTC691CSW#TRPBF is an open-drain logic output indicating VOUT power source: it pulls low when VOUT is powered by VCC, and goes high (open) when VOUT is powered by VBATT. It can sink 35mA and is commonly used to drive the base of an external PNP transistor to boost VOUT current beyond the internal 50mA limit. The LTC691CSW#TRPBF's BATT ON signal provides real-time visibility into backup mode activation without requiring additional sensing circuitry.

Does LTC691CSW#TRPBF support adjustable reset timeout, and how is it configured?

Yes - LTC691CSW#TRPBF supports adjustable reset timeout via the OSC SEL and OSC IN pins. With OSC SEL high, internal oscillator sets fixed 50ms typical timeout; with OSC SEL low, an external clock or capacitor on OSC IN determines timing using documented formulas. This allows designers to tailor reset duration to specific µP startup requirements. The LTC691CSW#TRPBF datasheet provides exact equations and example values for both modes, enabling precise timing control without firmware changes.