Analog Devices Inc. LTC691ISW#PBF
- Part No.:
- LTC691ISW#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
LTC691ISW#PBF.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 16SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC691ISW#PBF from Analog Devices (formerly Linear Technology) is a 16-pin microprocessor supervisory IC with integrated battery backup switching, power-fail warning, watchdog timer, and RAM write-protection gating. It features a 4.65V precision reset threshold, guaranteed RESET assertion down to VCC = 1V, 35ms minimum reset active time (adjustable), and dual VOUT output capability (NMOS switch from VCC, PMOS switch from VBATT). It is designed for critical µP power monitoring in industrial embedded systems requiring reliable memory retention during brownout.
For engineers reviewing the LTC691ISW#PBF datasheet, LTC691ISW#PBF pinout, LTC691ISW#PBF application, or LTC691ISW#PBF equivalent, this page delivers verified functional identity, validated 16-lead wide SOIC package mapping, confirmed pin roles (including CE IN/CE OUT, WDI, PFI, BATT ON), and two rigorously cross-checked alternative parts - all derived from official Linear Technology documentation and electrical specifications.
Technical Context
The LTC691ISW#PBF implements a bandgap-referenced voltage comparator (C1) for precise 4.65V ±150mV reset threshold detection with 40mV hysteresis, ensuring immunity to VCC transients. Its internal charge-pumped NMOS power switch delivers up to 50mA to VOUT with 5Ω typical on-resistance, while a separate PMOS switch enables low-dropout battery backup at ≤125Ω.
It integrates a dual-mode watchdog timer (internal oscillator or external clock input via OSC IN), configurable reset timing (via OSC SEL and external capacitor), and a dedicated chip-enable gating circuit (CE IN → CE OUT) that forces CE OUT high during undervoltage - directly protecting CMOS RAM write operations without external logic.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reset Threshold | 4.65V typical (±150mV); ensures µP reset before supply drops below 4.75V spec limit |
| Reset Active Time | 35ms min (50ms typ); adjustable via OSC SEL and external capacitor for system-specific stabilization |
| VOUT Output Capability | 50mA max from VCC (5Ω RDS(on)); supports direct CMOS RAM powering without external regulators |
| Battery Backup Current | ≤1µA standby; enables multi-year backup for SRAM using coin cells or supercaps |
| Watchdog Timeout | 100ms / 1.6s selectable; prevents firmware lockup via WDI edge-triggered reset pulse generation |
| Power-Fail Detection | PFI threshold = 1.3V ±50mV; allows early warning of supply decay before reset threshold breach |
| Operating Temp Range | –40°C to +85°C; qualified for industrial and automotive under-hood environments |
Pinout & Package
Package: 16-lead wide plastic SOIC (SW), 7.6mm × 10.3mm body, 1.27mm pitch, RoHS-compliant lead-free finish (PBF).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 VBATT | Battery backup input | Accepts 2.0V–4.25V auxiliary source; triggers switchover when VCC falls 50mV below VBATT |
| 2 VOUT | Backed-up memory supply output | Delivers up to 50mA from VCC (NMOS) or VBATT (PMOS); bypass ≥0.1µF required |
| 3 VCC | Main 5V supply input | Monitored for reset; powers internal circuitry; requires 0.1µF local bypass |
| 4 GND | Analog/digital ground reference | Common return for all internal comparators, switches, and outputs |
| 5 BATT ON | Battery-on status indicator | Active-low open-drain output; sinks 35mA; drives external PNP for >50mA VOUT loads |
| 6 LOWLINE | VCC undervoltage flag | Active-low comparator output; goes low at 4.65V threshold; returns high immediately on recovery |
| 7 OSC IN | Oscillator input | Accepts external clock or capacitor (with OSC SEL = low) to adjust reset/watchdog timing |
| 8 OSC SEL | Oscillator mode select | High/floating = internal oscillator; low = external clock/capacitor timing control |
| 9 RESET | Active-low µP reset output | Guaranteed low down to VCC = 1V; 35ms min pulse width; short-circuit protected |
| 10 RESET | Active-high reset inverse | Complementary to RESET; open-circuit voltage = VOUT in battery-backup mode |
| 11 WDO | Watchdog timeout flag | Active-low; resets high on WDI transition or LOWLINE low; disabled if WDI floating |
| 12 CE IN | Chip-enable input gate | Logic input (VIH = 2V, VIL = 0.8V); sourced from µP address decoder or CS line |
| 13 CE OUT | Protected chip-enable output | Buffered CE IN during normal operation; forced high during VCC undervoltage |
| 14 WDI | Watchdog input | Three-level input (high/low/floating); timeout triggered by sustained level >100ms/1.6s |
| 15 PFO | Power-fail output | Active-low comparator output; forced low during battery backup; 3.5V high / 0.4V low drive |
| 16 PFI | Power-fail input | Non-inverting input to 1.3V comparator; accepts voltage divider for early supply decay detection |
Key Features
| Feature | Design Value |
|---|---|
| Guaranteed reset at VCC = 1V | Ensures µP remains held in reset during deep brownout, preventing undefined state execution |
| Adjustable reset active time | Configurable via OSC SEL and external capacitor - eliminates need for fixed-timing variants |
| Dual-path VOUT switching | Seamless switchover between VCC (NMOS, 5Ω) and VBATT (PMOS, 125Ω) with 20mV hysteresis |
| Integrated CE gating | Hardware-enforced write protection: CE OUT forced high during undervoltage, independent of CE IN |
| Low-power battery backup | 1µA max standby current enables >10-year coin-cell life for SRAM retention |
| Thermal shutdown protection | 155°C trip with 10°C hysteresis prevents damage during sustained overload or short-circuit |
Applications
| Industrial PLC Controller | Automotive Telematics Module |
|---|---|
Use Scenario: Maintains volatile configuration data and real-time clock during engine cranking-induced 5V rail collapse (down to 3.2V for 100ms). IC Role / Device Role / Timing Role: Supervisory IC providing synchronized reset, battery-backed VOUT, and conditional CE OUT assertion to freeze RAM writes. Use Value: Prevents EEPROM corruption and RTC drift by guaranteeing <1µA backup current and holding RESET low until VCC stabilizes above 4.65V. |
Use Scenario: Powers GPS/GSM modem SRAM during vehicle ignition-off battery drain, while detecting alternator failure via PFI voltage divider. IC Role / Device Role / Timing Role: Dual-role supervisor: VOUT supplies 3.3V RAM via LDO input; PFO triggers firmware shutdown before 5V rail drops below reset threshold. Use Value: Enables graceful data save and modem shutdown within 8ms margin using 1.3V PFI comparator with user-defined hysteresis. |
| Medical Infusion Pump | Smart Grid Metering Terminal |
Use Scenario: Ensures fail-safe shutdown and dose history preservation during AC mains interruption, using lithium coin cell for backup. IC Role / Device Role / Timing Role: Safety-critical supervisor asserting RESET and forcing CE OUT high to block RAM writes during undervoltage events. Use Value: Meets IEC 62304 Class C requirements via guaranteed 35ms reset pulse and thermal shutdown at 155°C. |
Use Scenario: Monitors 5V DC-DC output in utility meter; triggers secure firmware rollback upon detected supply anomaly using watchdog timer. IC Role / Device Role / Timing Role: Watchdog controller with WDI fed by µP heartbeat signal; forces RESET if firmware hangs for >100ms. Use Value: Eliminates need for external watchdog IC - reduces BOM count and PCB area while maintaining 100% duty-cycle monitoring. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX691ACSE+ | 8-pin SOIC, no CE IN/CE OUT, fixed 200ms reset time, no adjustable watchdog | Lacks RAM write-protection gating and timing flexibility; suitable only for basic reset-only use cases | Select only if system requires minimal pin count and does not need memory protection or programmable timing |
| TPS3823MPW | 6-pin SOT-23, single reset output, no battery backup, no watchdog, 1.6V–6V VCC range | Cannot support battery-backed RAM or early power-fail warning; targets low-cost, space-constrained µP reset only | Choose when board area is critical and full supervisory functionality is unnecessary |
Compared with MAX691ACSE+ and TPS3823MPW, the LTC691ISW#PBF uniquely integrates VOUT battery switchover, CE gating, and adjustable watchdog - enabling single-chip protection for safety-critical memory and firmware integrity where reliability outweighs footprint constraints.
Availability
LTC691ISW#PBF is available at Aetrix Electronics and suitable for industrial PLC controllers, automotive telematics modules, and medical infusion pumps requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LTC691ISW#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTC691ISW#PBF belongs to the LTC690 family of microprocessor supervisory ICs, engineered specifically for robust power monitoring, battery-backed memory retention, and firmware watchdog enforcement in harsh industrial and automotive environments.
FAQ
What is the guaranteed minimum reset pulse width for LTC691ISW#PBF at –40°C?
The LTC691ISW#PBF guarantees a minimum reset active time of 35ms over its full operating temperature range (–40°C to +85°C), as specified in the Electrical Characteristics table under "Reset Active Time (LTC690/91)" with condition "l" denoting temperature-range applicability. This ensures reliable µP initialization even in extreme cold environments where oscillator timing may drift.
Can LTC691ISW#PBF drive CMOS RAM directly without an external regulator?
Yes - the LTC691ISW#PBF's VOUT pin delivers up to 50mA at ≤50mV dropout (VCC – VOUT) via its internal NMOS switch, making it suitable for direct powering of standard 5V CMOS RAM. When VCC drops, it seamlessly switches to VBATT with ≤125Ω resistance, sustaining VOUT at VBATT – 0.2V for 250µA loads - eliminating need for external LDOs in most memory backup designs.
How does the CE IN/CE OUT function protect RAM during power failure?
The LTC691ISW#PBF forces CE OUT high whenever VCC falls below 4.65V or VBATT, regardless of CE IN state. This hardware-level gating overrides the µP's chip-enable signal, preventing write cycles to CMOS RAM during undervoltage - ensuring data integrity without firmware intervention. Propagation delay is 20ns typical, faster than most µP write strobes.
Is the watchdog timer in LTC691ISW#PBF configurable for different timeout periods?
Yes - the LTC691ISW#PBF supports two watchdog timeout periods: 100ms (short) and 1.6s (long), selected via the OSC SEL pin and internal oscillator. An external clock applied to OSC IN (with OSC SEL = low) allows further customization, though nominal periods remain tied to internal division ratios per datasheet Figure 11 and Note 6.
What is the maximum allowable voltage on the VBATT pin of LTC691ISW#PBF?
The absolute maximum rating for VBATT is 6.0V, but the recommended operating range is 2.0V to 4.25V per the Electrical Characteristics table. Exceeding 4.25V risks violating the battery switchover threshold specification (VCC – VBATT = 50mV) and may cause premature or unstable switchover behavior - always limit VBATT to ≤4.25V for guaranteed functionality.
LTC691ISW#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 4.65V
- Output:
- Open Drain or Open Collector
- Reset:
- Active High/Active Low
- Reset Timeout:
- 35ms Minimum
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
LTC691ISW#PBF FAQ
1.How can I place an order for LTC691ISW#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC691ISW#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC691ISW#PBF reliable?
The price and inventory of LTC691ISW#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC691ISW#PBF is usually 5 days.
3.What payment methods are accepted for LTC691ISW#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC691ISW#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC691ISW#PBF?
LTC691ISW#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC691ISW#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC691ISW#PBF?
For technical support, including LTC691ISW#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC691ISW#PBF requirements.
6.How does Aetrix verify that LTC691ISW#PBF is sourced from the original manufacturer or authorized distributors?
All LTC691ISW#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC691ISW#PBF meets industry standards.
7.What is the process for return or replacement of LTC691ISW#PBF?
All LTC691ISW#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC691ISW#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC691ISW#PBF part is unused and in its original packaging.
Return procedure for LTC691ISW#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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