My Inquiry
My Account
Analog Devices Inc. LTC691ISW#TRPBF
- Part No.:
- LTC691ISW#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
LTC691ISW#TRPBF.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 16SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:3,171
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC691ISW#TRPBF from Analog Devices (formerly Linear Technology) is a 16-pin microprocessor supervisory IC with integrated battery backup, power-fail warning, watchdog timer, and RAM write-protection logic. It features a 4.65V precision reset threshold, guaranteed RESET assertion down to VCC = 1V, 35ms minimum reset active time (adjustable), 1.5mA max supply current, and dual VOUT switching (NMOS/PMOS) for CMOS RAM backup. It is used in industrial controllers and battery-powered embedded systems requiring reliable power monitoring and memory retention.
For engineers reviewing the LTC691ISW#TRPBF datasheet, LTC691ISW#TRPBF pinout, LTC691ISW#TRPBF application, or LTC691ISW#TRPBF equivalent, key selection considerations include its –40°C to +85°C industrial temperature rating, 16-lead wide SOIC (SW) package, adjustable reset timeout via OSC SEL/OSC IN, and dual active-low/high RESET outputs for flexible µP interface design.
Technical Context
The LTC691ISW#TRPBF integrates a bandgap voltage reference, precision comparator C1 (40mV hysteresis), charge-pumped NMOS switch (5Ω typical RDS(on), 50mA output), and PMOS battery switchover switch (125Ω, 250µA standby). Its internal oscillator sets reset timing and watchdog timeout, configurable via OSC SEL pin to select between fixed (50ms typical) or externally adjustable modes using OSC IN.
It implements conditional battery backup: when VCC drops below VBATT − 50mV, VOUT switches to VBATT; hysteresis prevents chatter. The CE IN/CE OUT gating circuit forces CE OUT high during undervoltage, unconditionally write-protecting external CMOS RAM. PFI/PFO provide user-defined power-fail detection referenced to a stable 1.3V internal reference.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reset Threshold | 4.65V typical (±50mV); ensures µP reset before VCC violates 5V ±5% spec. |
| Reset Active Time | 35ms min (50ms typ); adjustable via OSC IN; holds µP in reset until power stabilizes. |
| VOUT Output Capability | 50mA from VCC (5Ω RDS(on)), 250µA from VBATT (125Ω); powers backed-up RAM without external regulators. |
| Supply Current | 1.5mA max (active), 1µA max (battery backup); enables long-term battery operation. |
| Operating Temp Range | –40°C to +85°C (I-grade); qualified for industrial and automotive under-hood environments. |
| VBATT Input Range | 2.0V to 4.25V; supports Li-ion, coin cells, and supercapacitors for memory backup. |
| Watchdog Timeout | 100ms / 1.6s selectable; detects firmware hangs and forces system recovery. |
Pinout & Package
Package: 16-lead wide plastic SOIC (SW), 7.5mm × 10.3mm body, 1.27mm pitch, RoHS-compliant lead-free finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Primary 5V supply input | Bypassed with 0.1µF capacitor; powers all internal circuits except battery path. |
| VOUT | Backed-up memory supply output | Switches automatically between VCC (NMOS) and VBATT (PMOS); delivers up to 50mA. |
| VBATT | Battery backup input | Connects to auxiliary source; enables VOUT operation when VCC fails. |
| GND | Analog/digital ground reference | Common return for all internal blocks; must be low-impedance connection. |
| BATT ON | Battery status logic output | Active-low open-drain signal indicating VOUT sourced from VBATT; sinks 35mA. |
| LOWLINE | Active-low line-failure indicator | Complements RESET; goes low when VCC < 4.65V and returns high immediately on recovery. |
| OSC IN | Oscillator input/control | Accepts external clock or capacitor for adjustable reset/watchdog timing when OSC SEL = low. |
| OSC SEL | Oscillator mode selector | High/floating = internal oscillator; low = external timing control via OSC IN. |
| RESET | Active-low microprocessor reset | Guaranteed low down to VCC = 1V; minimum 35ms pulse width after power-up or watchdog timeout. |
| RESET | Active-high microprocessor reset | Inverted copy of RESET; simplifies interface to µPs requiring active-high reset. |
| WDO | Watchdog timeout indicator | Active-low output asserted when WDI remains static beyond timeout period. |
| CE IN | Chip enable input gate | Logic input from µP address decoder; controls CE OUT state during normal operation. |
| CE OUT | Protected chip enable output | Buffered CE IN during valid VCC; forced high during undervoltage to prevent RAM writes. |
| WDI | Watchdog input | Three-level input (low/high/floating); transitions reset watchdog timer; floating disables it. |
| PFI | Power-fail input | Non-inverting input to 1.3V-referenced comparator; monitors external voltage divider for early warning. |
| PFO | Power-fail output | Active-low open-drain output; signals impending supply collapse before RESET asserts. |
Key Features
| Feature | Design Value |
|---|---|
| Guaranteed RESET at VCC = 1V | Ensures deterministic µP shutdown even during deep brownout; eliminates race conditions in low-VCC states. |
| Adjustable reset active time | Configurable via OSC SEL/OSC IN; supports custom timing requirements without external RC networks. |
| Dual RESET outputs (active-low/high) | Eliminates need for external inverters; compatible with both legacy and modern µP reset architectures. |
| Conditional battery backup with hysteresis | 50mV switchover threshold + 20mV hysteresis prevents oscillation near VCC/VBATT crossover point. |
| Integrated RAM write protection | CE IN/CE OUT gating forces write-disable during undervoltage; protects data integrity without software intervention. |
| Low-power battery backup mode | 1µA max supply current with VCC = 0V; extends coin-cell life to >10 years in typical CMOS RAM applications. |
Applications
| Industrial PLC Controller | Automotive Telematics Unit |
|---|---|
Use Scenario: Maintains real-time clock and configuration memory during engine cranking-induced 3.3V rail collapse. IC Role / Device Role / Timing Role: Supervisory IC providing VOUT-backed RAM power, early PFO warning, and µP reset coordination. Use Value: Prevents loss of GPS log data and calibration settings during repeated cold-start voltage dips. |
Use Scenario: Powers SRAM during ignition-off battery drain while detecting main 12V supply decay. IC Role / Device Role / Timing Role: Battery switchover controller and power-fail monitor with watchdog supervision. Use Value: Enables graceful shutdown and secure data save before VCC falls below µP operational threshold. |
| Medical Infusion Pump | Smart Energy Meter |
Use Scenario: Preserves therapy history and dosage parameters during AC mains interruption. IC Role / Device Role / Timing Role: Dual-supply supervisor with guaranteed RESET at 1V and CE OUT write protection. Use Value: Meets IEC 62304 safety requirement for deterministic fault response and nonvolatile memory integrity. |
Use Scenario: Retains tariff schedules and consumption logs during grid outage with supercapacitor backup. IC Role / Device Role / Timing Role: High-accuracy power-fail detector (PFI/PFO) and low-quiescent VOUT regulator. Use Value: Achieves >10-year backup life with 0.1F supercapacitor due to 1µA battery-mode current. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX691ACSE+ | 8-pin SOIC, fixed 200ms reset timeout, no OSC IN/OSC SEL adjustability, no CE IN/CE OUT. | Lacks RAM write protection and adjustable timing; suitable only for basic reset-only use cases. | Select MAX691ACSE+ only if board space is constrained and advanced features are unnecessary. |
| TPS3823MPW | 6-pin SOT-23, single RESET output, no battery backup, no watchdog, no PFI/PFO, 1.6V–6V VCC range. | Designed for low-cost, low-pin-count reset supervision only; cannot replace battery backup or memory protection functions. | Choose TPS3823MPW only for simple reset generation where VOUT, VBATT, and CE gating are handled externally. |
Compared with LTC691ISW#TRPBF, MAX691ACSE+ offers smaller footprint but omits critical RAM protection and timing flexibility, while TPS3823MPW provides minimal reset functionality at lower cost but requires external circuitry for battery backup and power-fail warning-making LTC691ISW#TRPBF the only single-chip solution supporting full supervisory feature set in industrial temperature grade.
Availability
LTC691ISW#TRPBF is available at Aetrix Electronics and suitable for industrial PLC controllers, automotive telematics units, medical infusion pumps, and smart energy meters requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for LTC691ISW#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, formed through the acquisition of Linear Technology in 2017.
The LTC691ISW#TRPBF belongs to ADI's legacy Linear Technology supervisory IC family, designed specifically for robust power monitoring, battery-backed memory retention, and fail-safe microprocessor system control in harsh industrial and automotive environments.
FAQ
What is the guaranteed minimum VCC level at which LTC691ISW#TRPBF asserts RESET?
LTC691ISW#TRPBF guarantees RESET remains logic low down to VCC = 1V, ensuring reliable microprocessor hold-down during severe brownout conditions. This specification is tested and guaranteed over the full –40°C to +85°C operating temperature range, independent of load or VBATT voltage. The internal comparator and reset pulse generator maintain functional integrity even as VCC collapses, making LTC691ISW#TRPBF suitable for safety-critical applications where deterministic shutdown is mandatory.
How does LTC691ISW#TRPBF handle battery switchover between VCC and VBATT?
LTC691ISW#TRPBF uses two comparators with 50mV turn-on and 70mV turn-off thresholds and 20mV hysteresis to control NMOS (VCC→VOUT) and PMOS (VBATT→VOUT) switches. When VCC rises above VBATT + 50mV, VOUT connects to VCC; when VCC falls below VBATT + 50mV, VOUT switches to VBATT. This hysteresis prevents oscillation near the crossover point. The NMOS switch has ~5Ω RDS(on) (50mA capable), while the PMOS switch exhibits ~125Ω resistance (250µA standby).
Can LTC691ISW#TRPBF be used without a backup battery?
Yes, LTC691ISW#TRPBF operates fully without a backup battery: connect VBATT to GND and VOUT to VCC. All supervisory functions-including RESET, WDO, PFO, LOWLINE, and CE OUT gating-remain active. The battery switchover circuit is disabled, and VOUT is sourced solely from VCC. This configuration retains power-fail warning, watchdog supervision, and RAM write protection, making LTC691ISW#TRPBF viable for cost-sensitive applications where battery backup is optional.
What is the function of CE IN and CE OUT pins on LTC691ISW#TRPBF?
CE IN accepts a logic signal (e.g., from µP address decoder) to enable external memory; CE OUT is a buffered, fault-protected replica. When VCC ≥ 4.65V, CE OUT follows CE IN with 20ns propagation delay. When VCC drops below the reset threshold or VBATT, CE OUT is forced high-unconditionally disabling memory writes. This hardware-enforced write protection prevents data corruption during power instability, eliminating reliance on firmware-based safeguards in LTC691ISW#TRPBF designs.
Does LTC691ISW#TRPBF support adjustable watchdog timeout periods?
Yes, LTC691ISW#TRPBF supports two watchdog timeout periods-100ms (short) and 1.6s (long)-selected by the OSC SEL pin state. When OSC SEL is high or floating, the internal oscillator sets the timeout; when OSC SEL is low, an external clock applied to OSC IN determines timing. The timeout period immediately after reset is always 1.6s typical. This dual-mode flexibility allows LTC691ISW#TRPBF to adapt to varying firmware execution profiles without external components.
LTC691ISW#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 4.65V
- Output:
- Open Drain or Open Collector
- Reset:
- Active High/Active Low
- Reset Timeout:
- 35ms Minimum
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
LTC691ISW#TRPBF FAQ
1.How can I place an order for LTC691ISW#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC691ISW#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC691ISW#TRPBF reliable?
The price and inventory of LTC691ISW#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC691ISW#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC691ISW#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC691ISW#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC691ISW#TRPBF?
LTC691ISW#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC691ISW#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC691ISW#TRPBF?
For technical support, including LTC691ISW#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC691ISW#TRPBF requirements.
6.How does Aetrix verify that LTC691ISW#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC691ISW#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC691ISW#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC691ISW#TRPBF?
All LTC691ISW#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC691ISW#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC691ISW#TRPBF part is unused and in its original packaging.
Return procedure for LTC691ISW#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC691ISW#TRPBF Tags
-
MIC826SYMT-TR
Microchip Technology
-
APX803S-31SA-7
Diodes Incorporated
-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments
-
V6340RSP3B+
EM Microelectronic
-
EM6325CXSP5B-2.9+
EM Microelectronic
-
MCP120T-300I/TT
Microchip Technology
-
MCP130T-315I/TT
Microchip Technology
-
MCP120T-475I/TT
Microchip Technology
-
MCP111T-300E/TT
Microchip Technology
-
MCP120T-315I/TT
Microchip Technology
-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
