Analog Devices Inc. LTC693CN#PBF

Overview

LTC693CN#PBF from Analog Devices (formerly Linear Technology) is a 16-pin microprocessor supervisory IC with integrated battery backup switching, power-fail warning, watchdog timer, and RAM write-protection gating. It monitors VCC for reset assertion at 4.40V threshold, delivers up to 50mA from VOUT, guarantees RESET low down to VCC = 1V, and supports adjustable 140–280ms reset active time - used in automotive control units and industrial embedded systems requiring robust power sequencing.

For engineers reviewing the LTC693CN#PBF datasheet, LTC693CN#PBF pinout, LTC693CN#PBF application, or LTC693CN#PBF equivalent, key selection criteria include guaranteed reset assertion below 1V, 4.40V precision voltage monitoring, battery switchover hysteresis (20mV), PFI comparator response time (2μs falling), and CE IN/CE OUT memory protection gating with 20ns propagation delay.

Technical Context

The LTC693CN#PBF integrates five functional blocks: (1) a precision 4.40V reset comparator (C1) with 40mV hysteresis and 10μs response; (2) a dual-mode watchdog timer (internal oscillator or external clock input) with selectable 100ms/1.6s timeout; (3) a battery switchover circuit (C2) using NMOS/PMOS switches with 70mV power-up / 50mV power-down thresholds; (4) a 1.3V-referenced power-fail comparator (C3) with 2μs falling-edge response; and (5) CE IN/CE OUT logic gating with 20ns propagation delay and forced-high behavior during undervoltage.

It implements charge-pump-assisted NMOS VOUT switching (5Ω typical R_DS(on)) for low-dropout operation and uses a PMOS switch (125Ω slope) in battery backup mode, drawing ≤1μA standby current. All comparators and outputs are specified over 0°C to 70°C, matching the LTC693CN#PBF's commercial temperature grade.

Key Specifications

Pinout & Package

Package: 16-lead plastic DIP (N package), 0°C to 70°C operating range, θ_JA = 130°C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with MAX693ACPE+, the LTC693CN#PBF adds memory protection, battery boost capability, and adjustable reset timing - critical for data integrity in battery-backed systems; versus LTC693CS#PBF, it offers identical performance in a through-hole package enabling manual soldering and socket-based validation.

Availability

LTC693CN#PBF is available at Aetrix Electronics and suitable for automotive engine control units, industrial PLC memory backup, and medical infusion pump controllers requiring stable component supply across extended production lifecycles.

Supply support for LTC693CN#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices acquired Linear Technology in 2017 and maintains full product support, documentation, and manufacturing continuity for legacy Linear parts including the LTC693 series.

The LTC693 belongs to Linear's μP supervisory IC family, designed specifically for robust power monitoring, battery backup, and data integrity protection in safety-critical embedded systems operating from 0°C to 70°C.

FAQ

What is the guaranteed minimum VCC level at which LTC693CN#PBF asserts RESET?

The LTC693CN#PBF guarantees RESET remains logic low down to VCC = 1V, ensuring microprocessor reset integrity even during severe brownout conditions. This specification is tested and guaranteed across the full 0°C to 70°C operating range, and is independent of load or temperature drift. The LTC693CN#PBF achieves this via dedicated low-voltage biasing of its internal reset comparator and output driver stages.

How does LTC693CN#PBF implement battery switchover, and what are the voltage thresholds?

The LTC693CN#PBF uses an internal comparator (C2) to monitor the difference between VCC and VBATT. It connects VOUT to VCC when VCC exceeds VBATT by ≥70mV (power-up threshold), and switches to VBATT when VCC falls ≤50mV below VBATT (power-down threshold), with 20mV hysteresis to prevent chatter. The LTC693CN#PBF employs separate NMOS (for VCC-to-VOUT) and PMOS (for VBATT-to-VOUT) switches optimized for low dropout and leakage.

Can LTC693CN#PBF be used to protect EEPROM writes during power loss?

Yes - the LTC693CN#PBF provides dedicated CE IN and CE OUT pins that gate memory write-enable signals. When VCC drops below 4.40V or VBATT is engaged, CE OUT is forced high, disabling writes to EEPROM, SRAM, or NOVRAM regardless of CE IN state. This hardware-level protection requires no firmware intervention and operates with 20ns propagation delay, making the LTC693CN#PBF ideal for fail-safe data logging applications.

What is the function of the BATT ON pin on LTC693CN#PBF, and how is it used?

The BATT ON pin on LTC693CN#PBF is an open-collector logic output that goes low when VOUT is connected to VCC, and high when VOUT is switched to VBATT. It sinks up to 35mA and is designed to drive the base of an external PNP transistor, enabling higher-current battery backup delivery beyond the 50mA internal VOUT limit. This feature is unique to the LTC693CN#PBF among the LTC692/LTC693 family and is documented in Figure 2 of the datasheet.

Does LTC693CN#PBF support adjustable reset timeout, and how is it configured?

Yes - the LTC693CN#PBF supports adjustable reset active time from 140ms to 280ms, unlike the fixed 200ms timeout of the LTC692. Adjustment is achieved by connecting an external capacitor between OSC IN and GND while holding OSC SEL low; timing follows the formula t_RESET = 1.2 × R_OSC × C_OSC. This configurability allows precise alignment with microprocessor power-up requirements without adding discrete timing components.