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Analog Devices Inc. LTC693CSW
- Part No.:
- LTC693CSW
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
LTC693CSW.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 16SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:1,868
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Product details
Overview
LTC693CSW from Analog Devices (formerly Linear Technology) is an 8-pin SOIC microprocessor supervisory circuit with integrated battery backup switching, power-fail warning, watchdog timer, and RAM write-protection gating. It features a 4.40V precision reset threshold, guaranteed RESET assertion down to VCC = 1V, 1.5mA max supply current, 35ns CE gating delay, and 200ms fixed or adjustable reset timeout. It is used in automotive control units and industrial embedded systems requiring reliable power monitoring and nonvolatile memory protection.
For engineers reviewing the LTC693CSW datasheet, LTC693CSW pinout, LTC693CSW application, or LTC693CSW equivalent, key selection criteria include its dual reset outputs (RESET/RESET), BATT ON drive capability for external PNP transistors, programmable watchdog timeout via OSC SEL, and precise 1.3V PFI comparator for early power-fail detection in battery-backed systems.
Technical Context
The LTC693CSW integrates five functional blocks: a precision 4.40V reset comparator (C1) with 40mV hysteresis and 10μs response; a 1.3V reference-based power-fail comparator (C3); a charge-pumped NMOS main power switch (M1, RDS(on) ≈ 5Ω) and PMOS backup switch (M2, RDS(on) ≈ 125Ω); a 1.6s/100ms selectable watchdog timer with WDI transition detection; and CE IN/CE OUT logic gating with 20ns propagation delay.
Its battery switchover uses comparator C2 with 70mV power-up and 50mV power-down thresholds and 20mV hysteresis, enabling seamless VOUT sourcing from VCC or VBATT. The device operates across 0°C to 70°C, supports VCC = 4.5–5.5V and VBATT = 2.0–4.0V, and guarantees RESET low at VCC ≥ 1V with 200mV output voltage under 10μA sink.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reset Threshold | 4.40V typical; ensures reliable μP reset before 5V rail drops below 4.50V spec limit. |
| Reset Active Time | 200ms typical (fixed when OSC SEL high); provides sufficient stabilization time post-power-up. |
| VOUT Dropout | VCC – 0.05V at 1mA; enables low-loss CMOS RAM supply during normal operation. |
| Battery Switchover ΔV | 70mV (power-up), 50mV (power-down); prevents oscillation near VCC ≈ VBATT. |
| Supply Current | 1.5mA max (active), 1μA max (battery backup); minimizes primary power drain. |
| PFI Threshold | 1.30V typical; allows configurable early-warning detection via external resistor divider. |
| CE Propagation Delay | 20ns typical; ensures fast, glitch-free write-protection of RAM during brownout. |
Pinout & Package
Package: 16-lead plastic SOIC (SW package), 7.5mm × 10.3mm body, 1.27mm pitch, JEDEC MS-013AC compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (VBATT) | Backup battery input | Source for VOUT during VCC failure; accepts 2.0–4.0V; internal PMOS switch connects to VOUT when VCC < VBATT – 50mV. |
| 2 (VOUT) | Backed-up memory supply output | Delivers up to 50mA from VCC via NMOS switch (RDS(on) ≈ 5Ω) or from VBATT via PMOS switch (RDS(on) ≈ 125Ω). |
| 3 (VCC) | Main 5V supply input | Monitored by reset comparator C1; bypassed with 0.1μF capacitor; powers all internal circuits. |
| 4 (GND) | Ground reference | Common return for all analog and digital functions; must be low-impedance connection. |
| 5 (BATT ON) | Battery-on logic output | Sinks 35mA typical; drives base of external PNP transistor to extend VOUT current beyond 50mA. |
| 6 (LOW LINE) | Direct comparator C1 output | Active-low signal indicating VCC < 4.40V; returns high immediately when VCC rises above threshold. |
| 7 (OSC IN) | Oscillator input | Accepts external clock or 47pF capacitor to GND; selects watchdog timeout period when OSC SEL = 0V. |
| 8 (OSC SEL) | Oscillator mode select | High/float = internal oscillator (200ms reset, 1.6s/100ms watchdog); low = external clock/capacitor mode. |
| 9 (RESET) | Active-low μP reset output | Guaranteed low down to VCC = 1V; minimum 140ms pulse width; asserted on undervoltage or watchdog timeout. |
| 10 (RESET) | Active-high μP reset output | Inverse of RESET; open-circuit voltage equals VOUT in battery backup mode. |
| 11 (WDO) | Watchdog logic output | Active-low when WDI not toggled within timeout; set high on WDI transition or LOW LINE low. |
| 12 (CE IN) | Chip enable input | Logic input from μP address decoder; internally pulled up ~5μA; controls CE OUT gating. |
| 13 (CE OUT) | Chip enable output | Buffered CE IN during valid VCC; forced high during reset/brownout to write-protect RAM. |
| 14 (WDI) | Watchdog input | Three-level input (high/low/floating); floating disables watchdog; transitions reset timeout counter. |
| 15 (PFO) | Power-fail output | Active-low when PFI < 1.30V; forced low when VCC < VBATT; supports hysteresis via external R network. |
| 16 (PFI) | Power-fail input | Non-inverting input to comparator C3; referenced to internal 1.30V; ±25nA input bias current. |
Key Features
| Feature | Design Value |
|---|---|
| Guaranteed reset at VCC = 1V | Ensures μP remains held in reset during deep brownout, preventing undefined execution states. |
| Charge-pumped NMOS main switch | Achieves 5Ω RDS(on) and 50mA output without substrate injection-eliminates unwanted battery charging current. |
| Adjustable reset timeout (LTC693 only) | Enables system-specific reset duration tuning via external components, unlike fixed LTC692. |
| Dual reset outputs (RESET/RESET) | Provides both active-low and active-high signals, simplifying interface to diverse μP reset architectures. |
| Integrated CE IN/CE OUT gating | Automatically forces CE OUT high during brownout, eliminating need for external logic to protect RAM writes. |
| Thermal limiting with shutdown | Activates at ~155°C with 10°C hysteresis, protecting against sustained overload without latch-up. |
Applications
| Automotive Engine Control Unit (ECU) | Industrial Programmable Logic Controller (PLC) |
|---|---|
Use Scenario: Monitors 5V supply derived from vehicle battery; detects brownout during cranking and initiates safe shutdown. IC Role / Device Role / Timing Role: Supervisory IC providing reset assertion, power-fail warning (PFO), and RAM write-protection (CE OUT) during transient dips. Use Value: Prevents corrupted firmware execution and preserves EEPROM configuration data during 12V system fluctuations. |
Use Scenario: Powers and protects nonvolatile CMOS RAM in modular I/O backplane; maintains state during AC mains interruption. IC Role / Device Role / Timing Role: Dual-role supervisor: VOUT supplies backup RAM, while RESET/RESET coordinates cold-start sequencing with FPGA and MCU. Use Value: Enables <100ms failover to battery-backed memory, meeting IEC 61131-2 short-interruption immunity requirements. |
| Medical Infusion Pump Controller | Smart Meter Data Logger |
Use Scenario: Ensures deterministic reset and memory integrity during Li-ion battery discharge cycles and charger switchover. IC Role / Device Role / Timing Role: Battery switchover controller (VBATT → VOUT) + watchdog timer (WDI) for safety-critical task supervision. Use Value: Guarantees RAM retention down to 2.0V VBATT and triggers hard reset if motor control loop hangs. |
Use Scenario: Backs up real-time clock and tariff data storage during grid outages; monitors regulated 5V rail for early warning. IC Role / Device Role / Timing Role: Power-fail detector (PFI/PFO) + reset generator (RESET) + RAM supply (VOUT) in single-chip solution. Use Value: Delivers >10-year data retention using supercapacitor backup, with PFO interrupting μP 8ms before RESET asserts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX693ACPE+ | 8-pin PDIP only; no BATT ON output; fixed 200ms reset; no CE IN/CE OUT gating. | Lacks RAM write-protection logic and external transistor drive-requires additional discrete components for same functionality. | Select LTC693CSW when integrated CE gating and BATT ON drive reduce BOM count and PCB area. |
| TPS3823-44DBVR | Single 4.4V reset output; no battery backup, watchdog, or PFI/PFO; SOT-23-5 package. | Only provides basic reset supervision-cannot replace LTC693CSW in battery-switchover or power-fail warning roles. | Choose LTC693CSW for full-feature supervision where memory backup, early warning, and watchdog are mandatory. |
Compared with MAX693ACPE+ and TPS3823-44DBVR, the LTC693CSW uniquely combines reset, battery switchover, power-fail warning, watchdog, and RAM write-protection in one 16-pin SOIC-reducing system component count by ≥4 discrete ICs while supporting automotive and industrial temperature ranges.
Availability
LTC693CSW is available at Aetrix Electronics and suitable for automotive engine control units, industrial PLCs, medical infusion pump controllers, and smart meter data loggers requiring stable component supply and long-term lifecycle support.
Supply support for LTC693CSW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTC693CSW belongs to ADI's legacy Linear Technology supervisory IC product line, designed specifically for robust, feature-integrated power monitoring in safety-critical embedded systems where reliability, low quiescent current, and multi-function integration are essential.
FAQ
What is the guaranteed minimum VCC level at which LTC693CSW asserts RESET?
The LTC693CSW guarantees RESET remains logic low down to VCC = 1V with ISINK = 10μA, ensuring the microprocessor stays in a known reset state even during severe brownout conditions. This specification is explicitly tested and guaranteed over temperature, distinguishing LTC693CSW from many competitors that specify reset only down to 2.5V or higher. The internal comparator and reset pulse generator maintain functionality throughout this extended range, making LTC693CSW suitable for automotive cranking scenarios.
How does the LTC693CSW implement battery switchover, and what are the threshold voltages?
The LTC693CSW uses comparator C2 to monitor the difference between VCC and VBATT, connecting VOUT to the higher source. It switches from VBATT to VCC when VCC exceeds VBATT by 70mV (power-up threshold), and from VCC to VBATT when VCC falls below VBATT by 50mV (power-down threshold). The 20mV hysteresis prevents oscillation near the crossover point. During switchover, the NMOS main switch (M1) and PMOS backup switch (M2) operate with typical RDS(on) of 5Ω and 125Ω respectively, minimizing dropout in both modes.
Can the reset timeout of LTC693CSW be adjusted, and how does it differ from LTC692?
Yes, the LTC693CSW supports adjustable reset timeout via external components connected to OSC IN and OSC SEL, whereas the LTC692 has a fixed 200ms timeout. When OSC SEL is low, an external capacitor on OSC IN sets the timeout per the formula in the datasheet; when OSC SEL is high or floating, the internal oscillator fixes it at 200ms typical. This adjustability allows system designers to optimize reset duration for specific processor startup requirements-unlike the LTC692, which lacks this flexibility and omits the BATT ON and CE IN/CE OUT pins.
What is the function of the BATT ON pin on LTC693CSW, and why is it absent on LTC692?
The BATT ON pin on LTC693CSW is an open-drain logic output that sinks up to 35mA and is used to drive the base of an external PNP transistor, enabling VOUT currents beyond the internal 50mA NMOS switch limit. It is asserted high when VOUT is sourced from VBATT, allowing high-current battery backup. This pin is absent on the LTC692 because the LTC693 was designed as the enhanced variant with expanded battery-handling capability-LTC692 relies solely on its internal switches and requires external Schottky diodes for higher loads.
How does the CE IN/CE OUT gating circuit protect CMOS RAM during power failure?
The CE IN/CE OUT circuit on LTC693CSW buffers the microprocessor's chip-enable signal under normal conditions (VCC ≥ 4.40V) with 20ns propagation delay, but forces CE OUT high whenever VCC falls below the reset threshold or VBATT, regardless of CE IN state. This automatically disables RAM write access during brownout, preventing data corruption. Unlike software-based protection, this hardware gating is instantaneous and immune to processor lockup-ensuring memory integrity even if the μP fails mid-write cycle.
LTC693CSW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 4.4V
- Output:
- Open Drain or Open Collector
- Reset:
- Active High/Active Low
- Reset Timeout:
- 140ms Minimum
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
LTC693CSW FAQ
1.How can I place an order for LTC693CSW through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC693CSW on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC693CSW reliable?
The price and inventory of LTC693CSW are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC693CSW is usually 5 days.
3.What payment methods are accepted for LTC693CSW?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC693CSW transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC693CSW?
LTC693CSW orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC693CSW order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC693CSW?
For technical support, including LTC693CSW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC693CSW requirements.
6.How does Aetrix verify that LTC693CSW is sourced from the original manufacturer or authorized distributors?
All LTC693CSW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC693CSW meets industry standards.
7.What is the process for return or replacement of LTC693CSW?
All LTC693CSW units undergo pre-shipment inspection (PSI). If there is an issue with LTC693CSW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC693CSW part is unused and in its original packaging.
Return procedure for LTC693CSW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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