Analog Devices Inc. LTC693CSW#PBF

Overview

LTC693CSW#PBF from Analog Devices (formerly Linear Technology) is a 16-pin SOIC microprocessor supervisory IC with integrated battery backup switching, power-fail warning, watchdog timer, and RAM write-protection gating. It features a 4.40V precision reset threshold, guaranteed RESET assertion down to VCC = 1V, 200ms typical reset active time (adjustable), and delivers up to 50mA from VOUT with <5Ω on-resistance. It is used in automotive control units and industrial embedded systems requiring robust power monitoring and nonvolatile memory protection.

For engineers reviewing the LTC693CSW#PBF datasheet, LTC693CSW#PBF pinout, LTC693CSW#PBF application, or LTC693CSW#PBF equivalent, this page provides verified functional specifications, validated pin roles, confirmed battery switchover behavior, documented reset timing adjustability, and real-world use cases for microprocessor reset coordination, CMOS RAM write-protection, early power-fail warning, and watchdog timeout supervision.

Technical Context

The LTC693CSW#PBF integrates four independent comparator circuits: C1 monitors VCC against a 4.40V bandgap reference to drive RESET/LOW LINE; C2 compares VCC and VBATT with 70mV/50mV switchover thresholds and 20mV hysteresis to control NMOS/PMOS power switches; C3 compares PFI against a 1.3V internal reference to generate PFO; and a dedicated watchdog timer accepts WDI transitions and triggers RESET/WDO on timeout. All comparators operate across –40°C to 85°C with specified PSRR and response times.

Its dual-mode oscillator supports fixed 200ms reset timing (OSC SEL high/floating) or adjustable timing via external capacitor or clock on OSC IN, enabling configurable watchdog timeout periods of 100ms or 1.6s (typical). The CE IN/CE OUT gating path provides sub-35ns propagation delay and forces CE OUT high during undervoltage events to prevent RAM writes - a hardware-enforced data integrity mechanism independent of software state.

Key Specifications

Pinout & Package

Package: 16-lead plastic SO (SO-16), surface-mount, JEDEC MS-013AC compliant, θJA = 130°C/W on FR4 PCB.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with MAX693ACSE+ and TPS3823DBVR, the LTC693CSW#PBF uniquely integrates battery switchover, adjustable reset timing, hardware RAM write-protection, and dual-mode watchdog - making it irreplaceable in systems requiring coordinated power fail response, data integrity enforcement, and auxiliary power management.

Availability

LTC693CSW#PBF is available at Aetrix Electronics and suitable for automotive engine control units, industrial PLCs, medical infusion pump controllers, and smart meter data loggers requiring stable component supply and long-term lifecycle support.

Supply support for LTC693CSW#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors.

The LTC693CSW#PBF belongs to Linear's legacy μP supervisory product line, designed specifically for mission-critical embedded systems demanding simultaneous reset supervision, battery-backed memory protection, power-fail warning, and watchdog safety monitoring.

FAQ

What is the guaranteed minimum VCC level at which LTC693CSW#PBF asserts RESET?

The LTC693CSW#PBF guarantees RESET remains asserted down to VCC = 1V, ensuring the microprocessor stays in a known reset state even during severe brownout conditions. This specification is tested and guaranteed over temperature and process variation, and is critical for automotive and industrial applications where supply rails may dip unpredictably. The LTC693CSW#PBF achieves this via internal charge-pump circuitry that sustains logic functionality below standard CMOS thresholds.

Can LTC693CSW#PBF be used to protect EEPROM writes during power failure?

Yes - the LTC693CSW#PBF provides hardware-enforced write protection via its CE IN/CE OUT gating path. When VCC falls below 4.40V, CE OUT is forced high regardless of CE IN state, disabling chip select or write-enable inputs to EEPROM/NOVRAM. This occurs in under 35ns and requires no firmware intervention. The LTC693CSW#PBF thus prevents partial or corrupted writes during power collapse, a feature absent in basic reset-only supervisors.

How is the reset active time adjusted on LTC693CSW#PBF?

The LTC693CSW#PBF supports adjustable reset timing via the OSC IN and OSC SEL pins. With OSC SEL pulled low, an external capacitor (e.g., 47pF) between OSC IN and GND sets nominal reset duration; alternatively, an external clock applied to OSC IN allows precise timeout control. This differs from the fixed 200ms timing used when OSC SEL is high or floating. The LTC693CSW#PBF datasheet provides formulas linking capacitor value or clock frequency to resulting reset pulse width.

Does LTC693CSW#PBF support both primary and backup power sources simultaneously?

Yes - the LTC693CSW#PBF implements automatic, hysteresis-controlled switchover between VCC and VBATT. When VCC exceeds VBATT by ≥70mV, VOUT is sourced from VCC via an NMOS switch (5Ω typical R_DS(on)). When VCC drops to within 50mV of VBATT, VOUT seamlessly transfers to VBATT via a PMOS switch. This dual-rail operation is fully autonomous and requires no external control logic, making the LTC693CSW#PBF ideal for battery-backed memory retention.

What is the function of the BATT ON pin on LTC693CSW#PBF?

The BATT ON pin on the LTC693CSW#PBF is an open-drain logic output that goes low when VOUT is sourced from VCC and high when VOUT is sourced from VBATT. It can sink up to 35mA and is intended to drive the base of an external PNP transistor, enabling higher-current backup power delivery beyond the 50mA limit of the internal VOUT switch. This feature is unique to the LTC693 (not present in LTC692) and is explicitly documented in the LTC693CSW#PBF pin functions and Figure 2 of the datasheet.