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Analog Devices Inc. LTC693CSW#TRPBF
- Part No.:
- LTC693CSW#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
LTC693CSW#TRPBF.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 16SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:2,154
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Product details
Overview
LTC693CSW#TRPBF from Analog Devices (formerly Linear Technology) is a 16-pin SOIC microprocessor supervisory IC with integrated battery backup switching, power-fail warning, watchdog timer, and RAM write-protection gating. It monitors VCC for reset assertion at 4.40V threshold, delivers up to 50mA from VOUT, guarantees RESET low down to VCC = 1V, and provides adjustable 140–280ms reset active time - used in automotive ECUs and industrial controllers requiring fail-safe memory retention during brownout.
For engineers reviewing the LTC693CSW#TRPBF datasheet, LTC693CSW#TRPBF pinout, LTC693CSW#TRPBF application, or LTC693CSW#TRPBF equivalent, key selection criteria include its dual-reset outputs (RESET/RESET), battery switchover hysteresis (20mV), PFI comparator accuracy (±50mV over temp), CE IN/CE OUT propagation delay (20–45ns), and guaranteed operation across 0°C to 70°C.
Technical Context
The LTC693CSW#TRPBF integrates four independent functional blocks: (1) a precision 4.40V reset comparator (C1) with 40mV hysteresis and 10μs response; (2) a dual-mode watchdog timer supporting internal oscillator (100ms/1.6s timeout) or external clock input; (3) a charge-pumped NMOS switch (M1, RDS(on) ≈ 5Ω) and PMOS backup switch (M2, RDS(on) ≈ 125Ω); and (4) a dedicated power-fail comparator (C3) referenced to 1.3V with <8μs rising/falling response.
Its 16-pin SW package enables full feature set versus the 8-pin LTC692: dual reset outputs (active-low RESET and active-high RESET), LOW LINE status flag, OSC SEL configuration pin, and separate WDO watchdog output - all coordinated via internal state machine that forces CE OUT high during undervoltage to prevent RAM writes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reset Threshold | 4.40V typical (min 4.25V, max 4.50V) - ensures reliable μP reset before 5V rail violates ±10% spec. |
| VOUT Output Current | 50mA max from VCC - sufficient to power 64kB CMOS RAM without external boost. |
| Battery Switchover Hysteresis | 20mV - prevents oscillation when VCC ≈ VBATT during marginal brownout conditions. |
| Supply Current (Active) | 1.5mA max - enables low-power operation in battery-backed systems. |
| RESET Active Time | 140–280ms adjustable - meets JEDEC JESD78 latch-up immunity timing requirements. |
| PFI Input Threshold | 1.30V ±50mV - allows precise early-warning detection of 5V supply decay via external divider. |
| CE Propagation Delay | 20–45ns - ensures sub-50ns write-protection activation during VCC collapse. |
Pinout & Package
16-lead plastic SOIC (SW package), 7.5mm × 10.3mm body, 1.27mm pitch, RoHS-compliant matte tin finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (VBATT) | Backup Battery Input | Accepts 2.0–4.0V auxiliary source; triggers PMOS switchover when VCC falls 50mV below VBATT. |
| 2 (VOUT) | Backed-Up Memory Supply | Delivers regulated 5V-equivalent to RAM; switches between VCC (NMOS) and VBATT (PMOS) automatically. |
| 3 (VCC) | Main 5V Supply Input | Monitored for reset; powers internal circuitry and NMOS switch; requires 0.1μF local bypass. |
| 4 (GND) | Ground Reference | Common return for all analog/digital blocks; must be low-impedance connection to system ground plane. |
| 5 (BATT ON) | Battery-On Logic Output | Open-drain output indicating VOUT sourced from VBATT; sinks 35mA to drive external PNP base. |
| 6 (LOW LINE) | VCC Undervoltage Flag | Active-low signal asserting when VCC < 4.40V; returns high immediately upon recovery - no debounce delay. |
| 7 (OSC IN) | Oscillator Input | Accepts external clock (0–250kHz) or 47pF capacitor for programmable reset/watchdog timing. |
| 8 (OSC SEL) | Oscillator Mode Select | High/float = internal oscillator (fixed 200ms reset); low = external clock/capacitor mode (adjustable). |
| 9 (RESET) | Active-Low Reset Output | Guaranteed logic low down to VCC = 1V; drives μP /RESET pin directly; short-circuit protected. |
| 10 (RESET) | Active-High Reset Output | Inverse of RESET; used where host logic requires active-high reset assertion. |
| 11 (WDO) | Watchdog Timeout Output | Asserts low on WDI timeout; resets high on WDI transition or LOW LINE assertion - enables dual-fault detection. |
| 12 (CE IN) | Chip Enable Input | Accepts μP address decoder output; gated through CE OUT to prevent RAM writes during brownout. |
| 13 (CE OUT) | Gated Chip Enable Output | Buffered CE IN during normal operation; forced high during reset - disables RAM write access unconditionally. |
| 14 (WDI) | Watchdog Input | Three-level input (high/low/floating); timeout disabled when floating; transitions reset watchdog timer. |
| 15 (PFO) | Power-Fail Output | Open-drain output from PFI comparator; asserts low when PFI < 1.3V - triggers μP interrupt for shutdown. |
| 16 (PFI) | Power-Fail Input | Non-inverting input to 1.3V-referenced comparator; connected to resistor divider monitoring supply rail. |
Key Features
| Feature | Design Value |
|---|---|
| Dual Reset Outputs | Simultaneous active-low RESET and active-high RESET enable compatibility with diverse μP families and simplify level-shifting. |
| Adjustable Reset Timing | 140–280ms active window (via OSC IN/OSC SEL) satisfies JEDEC JESD78 and MIL-STD-883 timing compliance requirements. |
| Guaranteed Low-Voltage Reset | RESET remains valid down to VCC = 1V - ensures deterministic shutdown even during deep brownout or capacitor discharge. |
| Integrated RAM Write Protection | CE IN → CE OUT gating with 20ns propagation delay prevents corrupted writes during power collapse without external logic. |
| Thermal-Limited Battery Switching | Charge-pumped NMOS (M1) + PMOS (M2) architecture limits junction temperature to 155°C and eliminates substrate current injection into VBATT. |
Applications
| Automotive Engine Control Unit (ECU) | Industrial PLC Memory Backup |
|---|---|
Use Scenario: Maintains SRAM integrity during engine cranking-induced 5V brownouts (down to 3.2V for 100ms). IC Role / Device Role / Timing Role: Monitors VCC, asserts RESET/RESET, gates CE OUT to freeze RAM writes, and switches VOUT to VBATT within 20μs. Use Value: Prevents firmware corruption and preserves calibration data without external supervisors or discrete switches. |
Use Scenario: Powers nonvolatile RAM during AC mains failure in programmable logic controllers. IC Role / Device Role / Timing Role: Detects 5V rail decay via PFI divider, triggers PFO interrupt for controlled shutdown, and sustains VOUT from backup battery. Use Value: Enables >10-second safe shutdown window while maintaining real-time clock and I/O state. |
| Medical Infusion Pump Controller | Smart Meter Data Logger |
Use Scenario: Ensures fail-safe operation during battery swap in portable infusion devices. IC Role / Device Role / Timing Role: Uses BATT ON output to drive external PNP transistor, delivering >200mA to RAM during switchover. Use Value: Eliminates spurious resets and guarantees uninterrupted dose tracking during battery replacement. |
Use Scenario: Logs utility consumption data during grid outages using supercapacitor-backed VOUT. IC Role / Device Role / Timing Role: Configures OSC IN with 47pF capacitor to extend watchdog timeout to 1.6s, reducing false triggers from transient noise. Use Value: Achieves >72-hour backup runtime with <1μA standby current while maintaining accurate timestamping. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX693ACSE+ | 8-pin SOIC, fixed 200ms reset, no OSC SEL/WDI/PFO, 4.65V threshold | Lacks battery switchover control, watchdog, and power-fail warning - suitable only for basic reset-only use cases | Select when footprint and cost constrain design and full LTC693CSW#TRPBF feature set is unnecessary |
| TPS3823MPDBVR | 5-pin SOT-23, 3.08V threshold, no battery backup, no CE gating, 200ms fixed reset | Targeted at low-pin-count applications with single-supply monitoring only - no RAM protection or auxiliary power management | Choose for space-constrained designs where only primary supply monitoring is required |
Compared with MAX693ACSE+ and TPS3823MPDBVR, the LTC693CSW#TRPBF provides comprehensive power supervision including dual-reset outputs, adjustable timing, battery switchover hysteresis, and hardware-enforced RAM write protection - making it uniquely suited for safety-critical embedded systems requiring data integrity across power transitions.
Availability
LTC693CSW#TRPBF is available at Aetrix Electronics and suitable for automotive engine control units, industrial PLCs, medical infusion pumps, and smart meter data loggers requiring stable component supply and long-term lifecycle support.
Supply support for LTC693CSW#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors.
The LTC693 belongs to Linear's μP Supervisory family, designed specifically for fail-safe microprocessor systems requiring coordinated reset, memory protection, battery backup, and power-fail warning in harsh environments.
FAQ
What is the guaranteed minimum VCC voltage at which LTC693CSW#TRPBF asserts RESET?
The LTC693CSW#TRPBF guarantees RESET remains logic low down to VCC = 1V with ISINK = 10μA, ensuring deterministic microprocessor hold-down during deep brownout conditions. This specification is explicitly tested and guaranteed over the full 0°C to 70°C operating range, enabling robust operation in automotive cranking and industrial power sag scenarios where other supervisors fail.
How does LTC693CSW#TRPBF implement RAM write protection during power loss?
The LTC693CSW#TRPBF uses CE IN and CE OUT pins to gate memory access: when VCC drops below 4.40V, CE OUT is forced high regardless of CE IN state, disabling chip select or write-enable inputs to CMOS RAM. This hardware-level gating has 20–45ns propagation delay and operates independently of software - preventing corrupted writes even if the μP executes errant code during collapse.
Can LTC693CSW#TRPBF monitor both primary supply and backup battery voltage simultaneously?
Yes - the LTC693CSW#TRPBF monitors VCC for reset assertion and VBATT for switchover control, while the PFI pin can be configured (via external resistor divider) to monitor either the primary 5V rail or the backup battery voltage. Table 1 confirms PFI is ignored in battery backup mode, allowing dedicated battery health monitoring during normal operation without interference.
What is the maximum load current LTC693CSW#TRPBF can deliver from VOUT when powered by VBATT?
When operating in battery backup mode (VCC < VBATT), the LTC693CSW#TRPBF delivers VOUT from VBATT through a 125Ω PMOS switch, supporting up to 250μA continuous output current with <100mV dropout. The datasheet specifies VOUT = VBATT – 0.02V at 250μA, confirming suitability for low-power CMOS RAM and RTC circuits but not higher-current peripherals.
Does LTC693CSW#TRPBF support external adjustment of the power-fail warning threshold?
Yes - the PFI input accepts an externally generated voltage, allowing precise setting of the power-fail warning point via resistor dividers (e.g., Figures 8–9). The internal 1.3V reference is fixed, but the external network scales system voltage to match it; hysteresis can also be added using feedback resistors (R3/R4) between PFO and PFI to prevent chatter near trip point.
LTC693CSW#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 4.4V
- Output:
- Open Drain or Open Collector
- Reset:
- Active High/Active Low
- Reset Timeout:
- 140ms Minimum
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
LTC693CSW#TRPBF FAQ
1.How can I place an order for LTC693CSW#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC693CSW#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC693CSW#TRPBF reliable?
The price and inventory of LTC693CSW#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC693CSW#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC693CSW#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC693CSW#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC693CSW#TRPBF?
LTC693CSW#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC693CSW#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC693CSW#TRPBF?
For technical support, including LTC693CSW#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC693CSW#TRPBF requirements.
6.How does Aetrix verify that LTC693CSW#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC693CSW#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC693CSW#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC693CSW#TRPBF?
All LTC693CSW#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC693CSW#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC693CSW#TRPBF part is unused and in its original packaging.
Return procedure for LTC693CSW#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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