Analog Devices Inc. LTC6945IUFD#PBF

Overview

LTC6945IUFD#PBF from Analog Devices (formerly Linear Technology) is an ultralow-noise, 0.35–6 GHz integer-N phase-locked loop synthesizer IC with integrated VCO output divider (1–6), differential RF output buffer (–6 dBm to +3 dBm), and low-noise reference buffer (10–250 MHz, 0 dBm typical into 50 Ω). It delivers –226 dBc/Hz normalized in-band phase noise floor and –157 dBc/Hz wideband output phase noise floor, targeting high-performance LO generation in wireless infrastructure.

For engineers reviewing the LTC6945IUFD#PBF datasheet, LTC6945IUFD#PBF pinout, LTC6945IUFD#PBF application, or LTC6945IUFD#PBF equivalent, key selection criteria include its 28-pin 4 mm × 5 mm QFN package, SPI-controlled configuration, charge pump current programmability (250 µA–11.2 mA), 350 MHz–6 GHz VCO input range, and support for precise lock detection via STAT pin and status register.

Technical Context

The LTC6945IUFD#PBF implements a fully integrated PLL architecture comprising a reference divider (R = 1–1023), phase-frequency detector with configurable lock window (3–90 ns), charge pump with selectable clamps and mid-supply bias, integer feedback divider (N = 32–65535), and buffered VCO output divider (O = 1–6). Its differential RF output stage supports 50% duty cycle and software- or pin-controlled muting with 110 ns enable time.

It features independent supply domains: VREF+/VREFO+/VD+/VRF+/VVCO+ at 3.15–3.45 V (3.3 V nominal), and VCP+ at 3.15–5.25 V. All digital I/Os are CMOS-compatible (VIH = 1.55 V, VIL = 0.8 V), and the SPI interface supports read/write access to 16 registers for full configuration and status monitoring including LOCK/UNLOCK, THI/TLO clamp flags, and mute control.

Key Specifications

Pinout & Package

Package: 28-lead (4 mm × 5 mm) plastic QFN with exposed thermal pad (Pin 29 = GND). Requires soldering of exposed pad to PCB ground plane with multiple thermal vias per datasheet recommendation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar integer-N PLL synthesizer applications.

Compared with HMC703LP4E and ADF4371, the LTC6945IUFD#PBF uniquely combines ultralow integer-N phase noise, integrated reference buffer, and compact 28-pin QFN-making it optimal for space-constrained, high-performance LO generation where fractional-N complexity is unnecessary.

Availability

LTC6945IUFD#PBF is available at Aetrix Electronics and suitable for wireless infrastructure, high-speed data acquisition, and microwave radio applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for LTC6945IUFD#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices acquired Linear Technology in 2017 and maintains its high-performance analog and mixed-signal product lines, including precision timing ICs used in demanding communications and instrumentation systems.

The LTC6945IUFD#PBF belongs to Linear's ultralow-noise PLL synthesizer family, designed specifically for base station LO generation, high-speed converter clocking, and test equipment where phase noise, spurious performance, and integration density are critical.

FAQ

What is the maximum VCO input frequency supported by the LTC6945IUFD#PBF?

The LTC6945IUFD#PBF supports a VCO input frequency range of 350 MHz to 6000 MHz, as specified in the Electrical Characteristics table under fVCO parameter. This allows direct synthesis of microwave band LO signals without prescaling, and is validated across the full –40°C to +105°C operating temperature range.

Does the LTC6945IUFD#PBF include an integrated VCO?

No, the LTC6945IUFD#PBF does not include an integrated VCO. It is a PLL synthesizer IC that requires an external VCO connected to the VCO+ and VCO– pins. The device provides a low-noise VCO input buffer, integer feedback divider, and buffered output divider-but relies on an external high-performance VCO (e.g., Crystek CVCO55CL-0902-0928) for frequency generation.

How is RF output muting controlled on the LTC6945IUFD#PBF?

RF output muting on the LTC6945IUFD#PBF is controlled either by the MUTE pin (active-low CMOS input) or via SPI register bit PDALL. When asserted, muting reduces RF+ and RF– output power to –60 dBm within 110 ns while preserving internal bias conditions for rapid re-enablement (170 ns disable time), minimizing LO leakage during transmit/receive switching.

What reference input signal levels are acceptable for the LTC6945IUFD#PBF REF+ and REF– pins?

The LTC6945IUFD#PBF accepts differential reference inputs from 10 MHz to 250 MHz with a typical input signal level range of 0.5 VP-P to 2.7 VP-P (single-ended). For optimal phase noise performance, a CW signal ≥6 dBm into 50 Ω or a square wave ≥0.5 VP-P with slew rate ≥20 V/µs is recommended. BST and FILT[1:0] bits configure input buffer gain and filtering accordingly.

Can the LTC6945IUFD#PBF generate a 100 MHz reference output from its REFO pin?

Yes, the LTC6945IUFD#PBF can generate a 100 MHz reference output on the REFO pin. The REFO buffer supports 10–250 MHz output frequencies, delivering ~0 dBm into 50 Ω at 100 MHz (typical). It must be AC-coupled using a 22 nF capacitor and is disabled by default-enabled via PDREFO bit in the Power register (h02).