Analog Devices Inc. LTC6946IUFD-1#PBF
- Part No.:
- LTC6946IUFD-1#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 28-WFQFN Exposed Pad
- Datasheet:
-
LTC6946IUFD-1#PBF.pdf
- Description:
- IC CLK/FREQ SYNTH 28QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC6946IUFD-1#PBF from Analog Devices (formerly Linear Technology) is an ultralow-noise integer-N PLL synthesizer with integrated VCO, operating from 0.373GHz to 3.74GHz output frequency (via 1–6 programmable divider), featuring –226dBc/Hz normalized in-band phase noise floor, –157dBc/Hz wideband output phase noise floor, and SPI-compatible serial control. It serves as a high-stability local oscillator in wireless base station RF front-ends.
For engineers reviewing the LTC6946IUFD-1#PBF datasheet, LTC6946IUFD-1#PBF pinout, LTC6946IUFD-1#PBF application, or LTC6946IUFD-1#PBF equivalent, key selection criteria include its 28-pin 4mm × 5mm QFN package, VCO tuning sensitivity of 4.7–7.2%Hz/V, charge pump current range (250µA–11.2mA), and guaranteed operation from –40°C to 105°C junction temperature.
Technical Context
The LTC6946IUFD-1#PBF implements a fully integrated PLL architecture with reference divider (1–1023), phase-frequency detector (PFD), ultralow-noise charge pump, integer feedback divider (32–65535), and buffered VCO output divider (1–6). Its VCO requires no external tank components and performs internal calibration after power-on reset.
It supports configurable lock detection via STAT pin and SPI-accessible status register, selectable high/low voltage clamps on the charge pump for VCO monitoring, and output muting with 110ns enable time. The device uses differential RF outputs (RF+/RF–) with 136Ω internal pull-ups to VRF+ and operates with separate 3.3V digital/analog supplies and 5V VCO/charge pump rails.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Frequency Range | 0.373GHz to 3.74GHz (LTC6946-1 variant, via O_DIV = 1 to 6) |
| VCO Tuning Sensitivity | 4.7–7.2%Hz/V - determines loop filter gain and stability margin |
| Normalized In-Band Phase Noise Floor | –226dBc/Hz - sets close-in jitter performance for narrowband systems |
| Wideband Output Phase Noise Floor | –157dBc/Hz at 40MHz offset - critical for broadband receiver SNR |
| Charge Pump Current Range | 250µA to 11.2mA in 12 discrete steps - enables optimization of loop bandwidth and reference spur suppression |
| Reference Input Frequency | 10MHz to 250MHz - supports crystal oscillators and clock distribution networks |
| Supply Voltages | VREF+/VD+/VRF+ = 3.15–3.45V; VCP+/VVCO+ = 4.0–5.25V - mandates dual-rail PCB power design |
Pinout & Package
Package: 28-lead (4mm × 5mm) plastic QFN (UFD), exposed pad (Pin 29) soldered to ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VREFO+ (1) | REFO buffer supply | 3.15–3.45V rail requiring local 0.1µF bypass; powers low-noise reference output |
| REFO (2) | Reference output | Differential square wave output (≤250MHz), self-biased, requires 22nF AC coupling |
| STAT (3) | Status indicator | Configurable logic OR of LOCK/UNLOCK/ALC/thermal flags; used for system fault monitoring |
| CS (4) | SPI chip select | Active-low CMOS input initiating serial register access; must meet tCSS ≥10ns setup |
| SCLK (5) | SPI clock | CMOS input clocking SDI/SDO on rising edge; min 25ns high/low time required |
| SDI (6) | SPI data input | Serial command/data input; 6ns setup/hold timing relative to SCLK |
| SDO (7) | SPI data output | Three-state CMOS output; Hi-Z leakage ≤±1µA; requires >200kΩ pull-down if unused |
| VD+ (8) | Digital supply | 3.15–3.45V rail for SPI interface and control logic; local 0.1µF bypass essential |
| MUTE (9) | RF output disable | Active-low CMOS input; mutes RF± within 110ns while preserving VCO bias |
| GND (10,17,21,23,29) | Ground return | Multiple dedicated GND pins + exposed pad; all require low-inductance vias to ground plane |
| RF– / RF+ (11,12) | Differential RF output | Open-collector outputs with 136Ω internal pull-ups to VRF+; single-ended use requires 50Ω termination on unused pin |
| VRF+ (13) | RF output supply | 3.15–3.45V rail powering RF buffer; requires 0.01µF ceramic bypass adjacent to pin |
| BB (14) | RF reference bypass | Internal bias node; must be decoupled with 1.0µF capacitor to GND - no signal coupling allowed |
| TUNE (15) | VCO tuning voltage | Analog input connected to loop filter; 1.60–2.85V range per calibration spec; sensitive to noise |
| TB (16) | VCO bypass | Internal VCO bias node; requires 2.2µF capacitor to GND and short trace to CMA/CMB/CMC |
| CMC/CMB/CMA (18–20) | VCO bias inputs | Internal VCO core bias points; must tie directly to TB with minimal trace length; no routing underneath package |
| VVCO+ (22) | VCO supply | 4.75–5.25V rail; requires both 0.01µF and 1µF ceramic bypasses placed adjacent to pin |
| VCP+ (24) | Charge pump supply | 4.0–5.25V rail; 0.1µF bypass mandatory; supplies CP output stage and clamp circuitry |
| CP (25) | Charge pump output | Bidirectional current source/sink; connects to loop filter; voltage range limited by VCLMP(LO)/VCLMP(HI) |
| VREF+ (26) | Reference input supply | 3.15–3.45V rail for REF± buffer; 0.1µF bypass required; powers low-noise reference amplifier |
| REF– / REF+ (27,28) | Differential reference input | High-impedance, self-biased inputs; require 1µF AC coupling; single-ended use bypasses REF– to GND |
Key Features
| Feature | Design Value |
|---|---|
| Integrated VCO with zero external components | Eliminates discrete inductor/capacitor tank design, reduces BOM count and layout sensitivity |
| Programmable output divider (1–6) with 50% duty cycle | Enables flexible LO generation across sub-GHz to 3.74GHz without external dividers or synthesizers |
| Ultralow normalized in-band phase noise (–226dBc/Hz) | Directly improves EVM and ACLR in LTE/W-CDMA transmitters by reducing close-in jitter |
| SPI-compatible serial port with status register | Allows full configuration and real-time lock/fault monitoring in embedded systems without additional GPIO |
| Configurable RF output muting (110ns enable) | Supports fast TDD switching in FDD/TDD base stations and burst-mode radar applications |
| Separate 3.3V and 5V supply domains | Isolates noise-sensitive analog VCO/charge pump circuitry from digital control logic |
Applications
| Wireless Base Station Transceiver | Broadband Wireless Access |
|---|---|
Use Scenario: Generating local oscillator signals for upconversion in LTE macrocell and small-cell radio units operating in 700MHz–2.7GHz bands. IC Role / Device Role / Timing Role: Primary integer-N PLL synthesizer providing stable, low-phase-noise LO for direct-conversion transmitter mixers. Use Value: –226dBc/Hz normalized in-band phase noise ensures <–45dBc ACLR at 10MHz offset, meeting 3GPP TS 36.104 spectral mask requirements. | Use Scenario: Frequency synthesis for point-to-multipoint WiMAX and fixed wireless CPE operating in 2.3–2.7GHz licensed bands. IC Role / Device Role / Timing Role: High-stability LO generator for OFDM-based modems requiring low EVM under multipath fading. Use Value: Integrated VCO eliminates external tuning varactors, improving production yield and long-term frequency drift stability over temperature. |
| Military Secure Radio | Test and Measurement Equipment |
Use Scenario: LO source in software-defined radios (SDR) supporting frequency-hopping spread spectrum (FHSS) in 300MHz–3GHz tactical bands. IC Role / Device Role / Timing Role: Fast-locking PLL synthesizer enabling rapid channel switching (<100µs) with low spurious emissions. Use Value: –103dBc reference spurs and <0.17° RMS integrated phase noise (100Hz–40MHz) preserve signal fidelity during hopping transitions. | Use Scenario: Local oscillator in vector signal analyzers and arbitrary waveform generators requiring ultra-low phase noise across wide tuning ranges. IC Role / Device Role / Timing Role: Precision frequency source for calibration-grade instrumentation with sub-0.3° RMS jitter. Use Value: 28-pin QFN package with exposed thermal pad enables stable thermal performance during extended sweep measurements at full RF output power. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar integer-N PLL synthesizer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| HMC830LP6GE | Wider frequency range (25MHz–3GHz), higher max PFD frequency (100MHz), but higher normalized in-band phase noise (–219dBc/Hz) | Preferred for wideband test equipment requiring >100MHz reference inputs; less suitable for ultra-low-EVM cellular transmitters | Select HMC830LP6GE when reference frequency exceeds 250MHz or when wider PFD range is needed; verify loop filter redesign for phase noise trade-off |
| ADF4355-3BCPZ | Fractional-N architecture, wider output range (137.5MHz–6.8GHz), integrated LDOs, but higher wideband phase noise floor (–152dBc/Hz) | Better suited for multi-band lab equipment and agile frequency hopping; not optimized for static high-linearity transmitter LO | Choose ADF4355-3BCPZ for fractional-N flexibility and integrated power management; accept higher wideband noise if spurs are suppressed via dithering |
Compared with HMC830LP6GE and ADF4355-3BCPZ, the LTC6946IUFD-1#PBF delivers superior in-band phase noise and lower reference spurs, making it optimal for high-linearity cellular infrastructure where EVM and ACLR are critical, while requiring external loop filter design and dual-supply routing.
Availability
LTC6946IUFD-1#PBF is available at Aetrix Electronics and suitable for wireless base station transceivers, broadband wireless access nodes, military secure radios, and test and measurement equipment requiring stable component supply across industrial temperature ranges.
Supply support for LTC6946IUFD-1#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, formed through the acquisition of Linear Technology in 2017.
The LTC6946 product line was designed by Linear Technology specifically for high-frequency, low-phase-noise RF synthesis in demanding communications infrastructure, emphasizing integrated VCO performance, SPI configurability, and robust thermal packaging.
FAQ
What is the maximum output frequency supported by the LTC6946IUFD-1#PBF?
The LTC6946IUFD-1#PBF supports an output frequency range of 0.373GHz to 3.74GHz, corresponding to the LTC6946-1 variant. This range is achieved using the internal VCO (2.24GHz–3.74GHz) and the programmable output divider (O_DIV = 1 to 6). At O_DIV = 1, the maximum output frequency equals the maximum VCO frequency (3.74GHz); at O_DIV = 6, the minimum output is 0.373GHz. Operation outside this range requires selecting a different variant (e.g., LTC6946IUFD-4#PBF).
Does the LTC6946IUFD-1#PBF require external VCO components?
No, the LTC6946IUFD-1#PBF integrates a complete VCO core with no external tank components required. The VCO is internally calibrated after each power-on reset or software POR, eliminating the need for external inductors, varactors, or tuning capacitors. This integration reduces board area, improves production yield, and enhances long-term frequency stability over temperature and aging - a key differentiator versus discrete PLL+VCO solutions.
How does the charge pump current setting affect phase noise and reference spurs in the LTC6946IUFD-1#PBF?
In the LTC6946IUFD-1#PBF, higher charge pump current (up to 11.2mA) lowers the PLL loop filter impedance, increasing loop bandwidth and improving reference spur suppression - but also raises in-band phase noise due to increased PFD/CP noise contribution. Conversely, lower current (e.g., 250µA) reduces in-band noise but narrows loop bandwidth, potentially allowing larger reference spurs. The datasheet specifies –226dBc/Hz normalized in-band phase noise at ICP = 11.2mA, confirming optimal noise/spur trade-off at maximum current.
What is the purpose of the TUNE, TB, CMA, CMB, and CMC pins on the LTC6946IUFD-1#PBF?
These pins form the VCO bias network: TUNE is the analog tuning voltage input (1.60–2.85V); TB is the VCO's internal bias node, requiring a 2.2µF capacitor to GND; CMA/CMB/CMC are auxiliary VCO core bias inputs tied directly to TB with minimal trace length. Proper decoupling and routing of these pins - especially avoiding traces under the package - is essential to achieve the specified –157dBc/Hz wideband phase noise floor and prevent VCO pulling or instability.
Can the LTC6946IUFD-1#PBF operate with a single 3.3V supply?
No, the LTC6946IUFD-1#PBF requires three distinct supply domains: 3.15–3.45V for VREF+, VD+, VRF+, and VREFO+; 4.0–5.25V for VCP+; and 4.75–5.25V for VVCO+. Using a single 3.3V rail would violate absolute maximum ratings for VCP+ and VVCO+, risking permanent damage. A dual-rail power solution - typically 3.3V and 5V - is mandatory, with independent bypassing per supply pin as specified in the datasheet.
LTC6946IUFD-1#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Clock/Frequency Synthesizer (RF/IF), Integer N
- PLL:
- Yes
- Input:
- Clock
- Output:
- Clock
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 1:1
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 3.74GHz
- Divider/Multiplier:
- Yes/Yes
- Voltage - Supply:
- 3.15V ~ 5.25V
- Operating Temperature:
- -40°C ~ 105°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 28-QFN (4x5)
LTC6946IUFD-1#PBF FAQ
1.How can I place an order for LTC6946IUFD-1#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC6946IUFD-1#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC6946IUFD-1#PBF reliable?
The price and inventory of LTC6946IUFD-1#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC6946IUFD-1#PBF is usually 5 days.
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Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC6946IUFD-1#PBF?
For technical support, including LTC6946IUFD-1#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC6946IUFD-1#PBF requirements.
6.How does Aetrix verify that LTC6946IUFD-1#PBF is sourced from the original manufacturer or authorized distributors?
All LTC6946IUFD-1#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC6946IUFD-1#PBF meets industry standards.
7.What is the process for return or replacement of LTC6946IUFD-1#PBF?
All LTC6946IUFD-1#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC6946IUFD-1#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC6946IUFD-1#PBF part is unused and in its original packaging.
Return procedure for LTC6946IUFD-1#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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