My Inquiry
My Account
Analog Devices Inc. LTC6946IUFD-1#TRPBF
- Part No.:
- LTC6946IUFD-1#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 28-WFQFN Exposed Pad
- Datasheet:
-
LTC6946IUFD-1#TRPBF.pdf
- Description:
- IC CLK/FREQ SYNTH 28QFN
- Quantity:
- Payment:
- Shipping:
Inventory:4,578
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC6946IUFD-1#TRPBF from Analog Devices (formerly Linear Technology) is an ultralow-noise integer-N PLL synthesizer with integrated VCO, operating across 0.373GHz to 3.74GHz (VCO range 2.24–3.74GHz). It delivers –226dBc/Hz normalized in-band phase noise floor, –157dBc/Hz wideband output phase noise floor, and supports programmable output division (1–6) with 50% duty cycle. It is used in LTE/W-CDMA base station local oscillator generation where spectral purity and spurious suppression are critical.
For engineers reviewing the LTC6946IUFD-1#TRPBF datasheet, LTC6946IUFD-1#TRPBF pinout, LTC6946IUFD-1#TRPBF application, or LTC6946IUFD-1#TRPBF equivalent, this page provides verified technical context, validated pin functions, confirmed frequency coverage per variant, real-world phase noise performance at 10kHz/1MHz offsets, and SPI-controlled charge pump current tuning from 250µA to 11.2mA - all specific to the LTC6946IUFD-1#TRPBF variant.
Technical Context
The LTC6946IUFD-1#TRPBF implements a fully integrated PLL architecture with reference divider (1–1023), phase-frequency detector (PFD), ultralow-noise charge pump (250µA–11.2mA), integer feedback divider (32–65535), and on-die VCO calibrated for 2.24–3.74GHz operation. Its output divider (1–6) enables RF output frequencies from 0.373GHz to 3.74GHz without external components.
It features dual-mode charge pump clamps (VCLMP(HI)/VCLMP(LO)), configurable STAT pin status reporting, SPI-compatible serial interface (CS/SCLK/SDI/SDO), and RF output muting with 110ns enable time. The device operates across –40°C to +105°C with dedicated supply rails: 3.3V for digital/reference/RF sections and 5V for VCO/charge pump.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCO Frequency Range | 2.24GHz to 3.74GHz - defines usable LO synthesis band for LTE Band 1/3/7/20/28 uplink/downlink mixing. |
| Output Frequency Range | 0.373GHz to 3.74GHz - achieved via integer output divider (1–6), enabling flexible IF/RF generation. |
| Normalized In-Band Phase Noise Floor | –226dBc/Hz - sets fundamental limit on close-in jitter; enables <0.17° RMS integrated phase noise (100Hz–40MHz). |
| Charge Pump Current Range | 250µA to 11.2mA - 12 programmable settings; directly scales loop filter component values and lock time. |
| Reference Input Frequency | 10MHz to 250MHz - supports crystal oscillators, TCXOs, or clock generators; requires AC-coupling with 1µF capacitors. |
| RF Output Power (SE, fRF=900MHz) | –9.7dBm to 2.3dBm - selectable via RFO[1:0] bits; enables direct drive of mixer LO ports without amplification. |
| Supply Voltages | 3.3V (VREF+/VREFO+/VD+/VRF+), 5V (VVCO+/VCP+) - strict rail separation prevents noise coupling between analog/digital/VCO domains. |
Pinout & Package
28-lead (4mm × 5mm) plastic QFN (UFD package) with exposed thermal pad (Pin 29 = GND). Requires soldering exposed pad to PCB ground plane with multiple thermal vias for thermal management and low-inductance grounding.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VREFO+ (1) | REFO buffer supply | 3.3V rail for low-noise reference output; must be bypassed with 0.1µF ceramic capacitor to GND. |
| REFO (2) | Reference output | Buffered square wave (≤250MHz); self-biased, requires 22nF AC-coupling capacitor. |
| STAT (3) | Status indicator | Configurable OR of LOCK/UNLOCK/ALC/thermal flags; driven by internal register state. |
| CS (4) | SPI chip select | Active-low CMOS input; initiates SPI transaction when pulled low; timing min 10ns high/low. |
| SCLK (5) | SPI clock | CMOS input; data latched on rising edge; min 25ns high/low pulse width required. |
| SDI (6) | SPI data input | CMOS input; accepts 16-bit register writes; setup/hold time ≥6ns relative to SCLK. |
| SDO (7) | SPI data output | Three-state CMOS output; presents read data during CS low; Hi-Z leakage ≤±1µA. |
| VD+ (8) | Digital supply | 3.3V rail for SPI logic; bypass with 0.1µF ceramic capacitor near pin. |
| MUTE (9) | RF output control | Active-low CMOS input; mutes RF± outputs to –60dBm in 110ns; preserves internal bias. |
| GND (10,17,21,23,29) | Ground return | Multiple dedicated GND pins + exposed pad; all must connect to low-impedance ground plane. |
| RF– / RF+ (11,12) | Differential RF output | Open-collector outputs with 136Ω internal pull-ups to VRF+; require external 50Ω termination if single-ended. |
| VRF+ (13) | RF output supply | 3.3V rail for RF buffer; bypass with 0.01µF ceramic capacitor; separate from digital supplies. |
| BB (14) | RF reference bypass | Internal bias node; must be bypassed with 1.0µF ceramic capacitor to GND; no signal coupling. |
| TUNE (15) | VCO tuning voltage | Analog input (1.6–2.85V) for VCO frequency control; connects to external loop filter output. |
| TB (16) | VCO bypass | Internal VCO bias node; bypass with 2.2µF ceramic capacitor; ties to CMA/CMB/CMC. |
| CMC/CMB/CMA (18–20) | VCO bias inputs | Connect directly to TB with short trace; bypass jointly with 2.2µF capacitor; avoid routing under package. |
| VVCO+ (22) | VCO supply | 5V rail for VCO core; bypass with 0.01µF + 1µF ceramics; critical for phase noise performance. |
| VCP+ (24) | Charge pump supply | 5V rail for charge pump; bypass with 0.1µF ceramic; independent of VVCO+ for noise isolation. |
| CP (25) | Charge pump output | Bidirectional current source/sink; connects to loop filter; voltage range limited by VCLMP settings. |
| VREF+ (26) | Reference input supply | 3.3V rail for REF± buffer; bypass with 0.1µF ceramic; separate from VREFO+/VD+/VRF+. |
| REF– / REF+ (27,28) | Differential reference input | High-Z differential input (6.2–11.6kΩ); self-biased; requires 1µF AC-coupling; single-ended use possible. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated VCO with no external tank components | Eliminates discrete inductors/capacitors; reduces BOM count, layout area, and calibration effort. |
| Programmable output divider (1–6) with 50% duty cycle | Enables precise frequency scaling (e.g., 3.0GHz VCO → 1.0GHz RF output) while maintaining clean square wave. |
| Configurable charge pump current (250µA–11.2mA) | Allows optimization of loop bandwidth and lock time across diverse filter designs and PFD frequencies. |
| RF output muting with 110ns enable time | Supports fast TDD switching in LTE/WiMAX systems without disrupting internal VCO bias or lock state. |
| Low-noise reference output (REFO) with –155dBc/Hz @10MHz | Provides clean local clock for ADCs/DACs or secondary PLLs, reducing need for external buffers. |
| SPI interface with status register readback | Enables real-time monitoring of LOCK/UNLOCK/ALC/thermal conditions without external logic. |
Applications
| Wireless Base Station LO Generation | Broadband Wireless Access Transceiver |
|---|---|
|
Use Scenario: Generating local oscillator signals for LTE FDD/TDD macrocell transceivers operating in Band 1 (2100MHz), Band 3 (1800MHz), and Band 7 (2600MHz). IC Role / Device Role / Timing Role: Primary integer-N PLL synthesizer providing ultralow-phase-noise LO to quadrature modulators and demodulators. Use Value: Achieves –157dBc/Hz wideband phase noise floor and –103dBc spurious suppression, meeting 3GPP ACLR requirements without additional filtering. |
Use Scenario: Frequency synthesis in point-to-point microwave backhaul radios (e.g., 3.5GHz/5.8GHz ETSI bands) requiring rapid frequency agility and low EVM. IC Role / Device Role / Timing Role: High-speed reconfigurable LO generator supporting OFDM symbol timing and carrier recovery loops. Use Value: 240MHz frequency step transient response (G12) and 110ns RF mute enable time support dynamic channel switching and TDD guard intervals. |
| Military Secure Radio Synthesizer | Test & Measurement Signal Source |
|
Use Scenario: LO generation in software-defined radios (SDR) for SATCOM and tactical HF/VHF/UHF systems requiring high spectral purity and anti-jam resilience. IC Role / Device Role / Timing Role: Core frequency synthesizer in wideband transceiver front-end, driving mixers and ADC clock trees. Use Value: –226dBc/Hz normalized in-band phase noise floor minimizes reciprocal mixing in congested RF environments. |
Use Scenario: Precision signal generation in benchtop RF signal analyzers and vector network analyzers requiring stable, low-spur outputs. IC Role / Device Role / Timing Role: Reference-grade synthesizer module delivering calibrated RF tones with traceable phase noise performance. Use Value: Verified –274dBc/Hz normalized 1/f noise and <0.17° RMS integrated phase noise (100Hz–40MHz) meet metrology-grade specifications. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar integer-N PLL synthesizer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| HMC830LP6GE | Wider VCO range (2.2–10.5GHz), higher max PFD frequency (150MHz), but higher typical in-band phase noise (–215dBc/Hz vs –226dBc/Hz). | Supports Ka-band applications beyond LTC6946IUFD-1#TRPBF's 3.74GHz limit; less suitable for sub-1GHz IF generation due to higher minimum divide ratio. | Select HMC830LP6GE when extending beyond 3.74GHz or requiring >100MHz PFD; verify loop filter redesign for higher charge pump current (up to 5mA). |
| ADF4351BCPZ | Fractional-N architecture, wider output range (35–4400MHz), but higher wideband phase noise (–150dBc/Hz vs –157dBc/Hz) and no integrated REFO buffer. | Better suited for wideband scanning and frequency hopping; lacks dedicated low-noise reference output needed for multi-PLL synchronization. | Select ADF4351BCPZ for cost-sensitive broadband applications where fractional resolution is required; add external buffer if REFO functionality is needed. |
Compared with HMC830LP6GE and ADF4351BCPZ, the LTC6946IUFD-1#TRPBF offers superior in-band phase noise and integrated reference buffering - critical for high-order modulation schemes - while trading off maximum frequency range and fractional-N flexibility.
Availability
LTC6946IUFD-1#TRPBF is available at Aetrix Electronics and suitable for wireless infrastructure, military radio, and test equipment applications requiring stable component supply, long-term lifecycle support, and guaranteed lot traceability.
Supply support for LTC6946IUFD-1#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full product support, documentation, and manufacturing continuity for the LTC6946 family.
The LTC6946 series was designed specifically for high-performance wireless infrastructure LO synthesis, emphasizing ultralow phase noise, integrated VCO calibration, and robust SPI control - targeting base stations, microwave links, and secure comms systems.
FAQ
What is the exact VCO frequency range supported by the LTC6946IUFD-1#TRPBF?
The LTC6946IUFD-1#TRPBF supports a VCO frequency range of 2.24GHz to 3.74GHz, as specified in the "Available Options" table and confirmed in the Electrical Characteristics section (fVCO parameter, LTC6946-1 variant). This range is factory-calibrated and does not require external VCO tank components. Operation outside this band is not guaranteed and may result in loss of lock or degraded phase noise.
How does the LTC6946IUFD-1#TRPBF achieve its –226dBc/Hz normalized in-band phase noise floor?
The LTC6946IUFD-1#TRPBF achieves –226dBc/Hz normalized in-band phase noise floor through a combination of ultralow-noise charge pump design, optimized PFD architecture, and highly linear VCO tuning characteristics. This value is measured inside the loop bandwidth with ICP = 11.2mA, fPFD = 250kHz, and loop bandwidth = 25kHz, as documented in Note 11 of the Electrical Characteristics table.
Can the LTC6946IUFD-1#TRPBF generate an RF output at exactly 900MHz, and what is the expected output power?
Yes, the LTC6946IUFD-1#TRPBF can generate 900MHz RF output using VCO = 2.7GHz with output divider = 3 (2.7GHz ÷ 3 = 900MHz), which falls within its supported 0.373–3.74GHz output range. At fRF = 900MHz, RFO[1:0] = 0, and 50Ω load, the typical single-ended output power is –9.7dBm, as specified in the Electrical Characteristics table under PRF(SE).
What are the supply voltage requirements for the LTC6946IUFD-1#TRPBF, and why are they split across multiple rails?
The LTC6946IUFD-1#TRPBF requires three distinct supply domains: 3.3V (±150mV) for VREF+, VREFO+, VD+, and VRF+; 5V (±250mV) for VVCO+ and VCP+; and GND connections on Pins 10, 17, 21, 23, and 29. This separation isolates noise-sensitive analog (VCO, charge pump) and digital (SPI, reference) circuits, preserving phase noise performance and preventing digital switching noise from modulating the VCO.
Is the LTC6946IUFD-1#TRPBF pin-compatible with other variants in the LTC6946 family, such as LTC6946IUFD-3#TRPBF?
Yes, all UFD-package variants (LTC6946IUFD-1#TRPBF through LTC6946IUFD-4#TRPBF) share identical 28-pin QFN footprints, pin assignments, and electrical interfaces. The only functional difference is the factory-trimmed VCO frequency range (2.24–3.74GHz for -1, 3.84–5.79GHz for -3), making them drop-in replacements at the board level when frequency requirements align.
LTC6946IUFD-1#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Clock/Frequency Synthesizer (RF/IF), Integer N
- PLL:
- Yes
- Input:
- Clock
- Output:
- Clock
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 1:1
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 3.74GHz
- Divider/Multiplier:
- Yes/Yes
- Voltage - Supply:
- 3.15V ~ 5.25V
- Operating Temperature:
- -40°C ~ 105°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 28-QFN (4x5)
LTC6946IUFD-1#TRPBF FAQ
1.How can I place an order for LTC6946IUFD-1#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC6946IUFD-1#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC6946IUFD-1#TRPBF reliable?
The price and inventory of LTC6946IUFD-1#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC6946IUFD-1#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC6946IUFD-1#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC6946IUFD-1#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC6946IUFD-1#TRPBF?
LTC6946IUFD-1#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC6946IUFD-1#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC6946IUFD-1#TRPBF?
For technical support, including LTC6946IUFD-1#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC6946IUFD-1#TRPBF requirements.
6.How does Aetrix verify that LTC6946IUFD-1#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC6946IUFD-1#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC6946IUFD-1#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC6946IUFD-1#TRPBF?
All LTC6946IUFD-1#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC6946IUFD-1#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC6946IUFD-1#TRPBF part is unused and in its original packaging.
Return procedure for LTC6946IUFD-1#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC6946IUFD-1#TRPBF Tags
-
CD74HCT4046AM96
Texas Instruments
-
MC14046BDWR2G
onsemi
-
501MILFT
Renesas
-
CD74HC7046AM
Texas Instruments
-
CDCVF2505PWR
Texas Instruments
-
RC19004A100GNL#KB0
Renesas
-
SI5351A-B-GTR
Skyworks Solutions Inc.
-
CY2305SXI-1T
Infineon Technologies
-
570BILFT
Renesas
-
CDCE913PWR
Texas Instruments
-
CY2305SXI-1HT
Infineon Technologies
-
DS1086LU+T
Analog Devices Inc./Maxim Integrated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
