Analog Devices Inc. LTC6946IUFD-2#PBF
- Part No.:
- LTC6946IUFD-2#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 28-WFQFN Exposed Pad
- Datasheet:
-
LTC6946IUFD-2#PBF.pdf
- Description:
- IC CLK/FREQ SYNTH 28QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC6946IUFD-2#PBF from Analog Devices (formerly Linear Technology) is an ultralow-noise integer-N PLL synthesizer with integrated VCO, operating across 3.08GHz to 4.91GHz (VCO range) and delivering RF output from 0.513GHz to 2.455GHz via programmable 1–6 divider. It features –226dBc/Hz normalized in-band phase noise floor, 11.2mA adjustable charge pump current, and SPI-compatible serial control - deployed in LTE/W-CDMA base station local oscillators.
For engineers reviewing the LTC6946IUFD-2#PBF datasheet, LTC6946IUFD-2#PBF pinout, LTC6946IUFD-2#PBF application, or LTC6946IUFD-2#PBF equivalent, key selection criteria include its guaranteed VCO frequency band (LTC6946-2), integrated loop filter interface (CP, TUNE), differential RF output architecture (RF+/RF–), and temperature-stable operation from –40°C to 105°C in the 4mm × 5mm QFN package.
Technical Context
The LTC6946IUFD-2#PBF implements a fully integrated PLL architecture with reference divider (R = 1–1023), phase-frequency detector (PFD), ultralow-noise charge pump (ICP = 0.25–11.2mA), integer feedback divider (N = 32–65535), and on-die VCO calibrated for 3.08–4.91GHz operation. Its output divider (O = 1–6) enables precise sub-GHz to mid-GHz RF synthesis without external components.
It supports dual-mode VCO tuning sensitivity (4.7–7.0%Hz/V), configurable lock window width (3–90ns), and low-jitter RF output with 50% duty cycle. The device uses separate supply domains (3.3V for digital/reference/RF, 5V for VCO/charge pump) and integrates status reporting via STAT pin and SPI-accessible register.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCO Frequency Range | 3.08GHz to 4.91GHz - defines usable RF synthesis band for LTC6946-2 variant; enables coverage of PCS, W-CDMA, and WiMAX bands. |
| Output Divider Range | 1 to 6 - provides six discrete RF output frequencies per VCO setting; ensures 50% duty cycle and supports wideband receiver LO generation. |
| Normalized In-Band Phase Noise Floor | –226dBc/Hz - sets ultra-low close-in noise benchmark; critical for high-order QAM modulation in wireless infrastructure. |
| Charge Pump Current Range | 0.25mA to 11.2mA - 12-step programmable ICP allows loop bandwidth optimization across PFD frequencies (100kHz–100MHz). |
| Reference Input Frequency | 10MHz to 250MHz - supports crystal oscillator, TCXO, or clock generator inputs; requires AC-coupling and self-biasing per REF+/REF– pins. |
| Operating Temperature Range | –40°C to 105°C - qualified for industrial and outdoor base station environments; junction-limited to 125°C max. |
| Supply Voltages | 3.3V (VREF+/VREFO+/VD+/VRF+), 5V (VVCO+/VCP+) - segregated rails minimize noise coupling between digital, RF, and VCO domains. |
Pinout & Package
Package: 28-lead (4mm × 5mm) plastic QFN (UFD), exposed pad (Pin 29) soldered to ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VREFO+ (1) | REFO buffer supply | 3.3V rail dedicated to low-noise reference output; bypass with 0.1µF capacitor to minimize REFO phase noise degradation. |
| REFO (2) | Reference output | Buffered square-wave output (≤250MHz); self-biased, requires 22nF AC-coupling; used for system clock distribution or secondary PLL reference. |
| STAT (3) | Status indicator | Configurable open-drain output reflecting LOCK/UNLOCK/ALC/thermal flags; enables real-time PLL health monitoring without SPI polling. |
| CS (4) | SPI chip select | Active-low CMOS input initiating SPI frame; must meet tCSS ≥10ns setup to SCLK rising edge for reliable register access. |
| SCLK (5) | SPI clock | CMOS input clocking SDI/SDO data; minimum 25ns high/low time supports up to ~20MHz SPI rate. |
| SDI (6) | SPI data input | Serial command/data input; latched on SCLK rising edge; requires tCS ≥6ns setup and tCH ≥6ns hold relative to SCLK. |
| SDO (7) | SPI data output | Three-state CMOS output; drives data on SCLK falling edge; Hi-Z when CS high; 30pF load limits tDO ≤16ns propagation delay. |
| VD+ (8) | Digital supply | 3.3V power for SPI interface and status logic; independent from analog supplies to prevent digital switching noise injection. |
| MUTE (9) | RF output disable | Active-low CMOS input disabling RF+/RF– outputs within 170ns; preserves internal bias for fast re-enable (<110ns mute enable). |
| GND (10,17,21,23,29) | Ground return | Multiple dedicated GND pins + exposed pad ensure low-inductance return paths; Pin 29 (exposed pad) must be soldered to PCB ground plane. |
| RF– / RF+ (11,12) | Differential RF output | Open-collector outputs with 136Ω internal pull-ups to VRF+; require external 50Ω termination per leg when used single-ended; support 0.513–2.455GHz output. |
| VRF+ (13) | RF output supply | 3.3V rail powering RF buffer stage; bypass with 0.01µF ceramic capacitor near pin to suppress high-frequency supply noise. |
| BB (14) | RF reference bypass | Internal bias node requiring 1.0µF ceramic capacitor to GND; no signal coupling permitted - isolation prevents VCO phase noise modulation. |
| TUNE (15) | VCO tuning voltage | Analog input (1.60–2.85V) controlling VCO frequency; connects directly to loop filter output; sensitive to noise - requires clean, low-impedance path. |
| TB (16) | VCO bypass | Internal VCO core bias node; bypass with 2.2µF capacitor; ties to CMA/CMB/CMC; trace routing under package prohibited for optimal phase noise. |
| CMC/CMB/CMA (18–20) | VCO bias inputs | Internal VCO tuning nodes; short-trace connection to TB and 2.2µF bypass required; layout under package affects 1/f noise performance. |
| VVCO+ (22) | VCO supply | 5V rail powering VCO core; bypass with 0.01µF + 1µF ceramics; higher voltage improves VCO tuning linearity and reduces 1/f noise. |
| VCP+ (24) | Charge pump supply | 5V rail for charge pump; bypass with 0.1µF ceramic; clamping voltages (VCLMP(HI)/VCLMP(LO)) enable VCO monitoring during calibration. |
| CP (25) | Charge pump output | Bidirectional current source/sink driving loop filter; connects to TUNE via RC network; polarity and magnitude set by PFD state and ICP setting. |
| VREF+ (26) | Reference input supply | 3.3V rail for REF+/REF– buffer; bypass with 0.1µF ceramic; BST bit configures input gain to prevent saturation at high VREF levels. |
| REF– / REF+ (27,28) | Differential reference input | High-Z (6.2–11.6kΩ), self-biased inputs; require 1µF AC-coupling; single-ended use needs REF– bypassed to GND with 1µF (or 47pF if >2.7VP-P). |
Key Features
| Feature | Design Value |
|---|---|
| Integrated VCO with auto-calibration | Eliminates external tank components and factory trimming; achieves target frequency after power-on-reset without host intervention. |
| Programmable output divider (1–6) | Enables flexible LO generation across multiple IF stages; maintains 50% duty cycle and consistent output impedance (111–159Ω) across all ratios. |
| Configurable charge pump current (0.25–11.2mA) | Supports loop bandwidth scaling from kHz to MHz; allows optimization of lock time vs. phase noise trade-off for specific PFD frequencies. |
| Dual-voltage charge pump clamps | Allows monitoring of VCO tuning voltage during calibration (via VCLMP(HI)/VCLMP(LO)); simplifies closed-loop VCO characterization. |
| SPI-compatible serial interface | Enables full register configuration (R/N/O dividers, ICP, FILT, BST, lock window) and status readback using standard 4-wire protocol. |
| Low-noise reference output (REFO) | Delivers –155dBc/Hz phase noise at 10MHz; suitable as clean clock source for ADCs, DACs, or secondary synthesizers in multichip systems. |
Applications
| Wireless Base Station LO Generation | Broadband Wireless Access Transceivers |
|---|---|
|
Use Scenario: Generating local oscillator signals for LTE FDD/TDD and W-CDMA uplink/downlink mixing in macrocell and microcell base stations. IC Role / Device Role / Timing Role: Integer-N PLL synthesizer providing stable, low-phase-noise RF carriers from 1.8GHz to 2.6GHz (via O=2,3) and 3.5GHz (O=1) using LTC6946IUFD-2#PBF's 3.08–4.91GHz VCO. Use Value: –226dBc/Hz normalized in-band phase noise enables 256-QAM constellations with EVM <2.5%; integrated VCO eliminates external coil calibration and reduces BOM count by 4+ components. |
Use Scenario: Providing tunable LO for point-to-point microwave backhaul radios operating in 3.5GHz, 5.8GHz, and 6.4GHz licensed bands. IC Role / Device Role / Timing Role: Synthesizer generating 3.5GHz (O=1), 1.75GHz (O=2), or 1.17GHz (O=3) outputs from same VCO core; MUTE pin enables fast channel switching <200ns. Use Value: Output divider flexibility supports multi-band hardware reuse; 0.513–2.455GHz output range covers WiMAX IEEE 802.16d/e channels without redesign. |
| Military & Secure Radio Front Ends | Test and Measurement Signal Sources |
|
Use Scenario: Frequency-agile transceiver in SATCOM terminals and tactical radios requiring rapid frequency hopping and low probability of intercept (LPI). IC Role / Device Role / Timing Role: High-speed PLL with 240MHz frequency step transient (G12) and programmable lock window enabling deterministic hop timing under SPI control. Use Value: 110ns mute enable and 170ns mute disable allow seamless gapless transmission; –103dBc spurious suppression meets MIL-STD-461E emissions requirements. |
Use Scenario: Core frequency source in benchtop spectrum analyzers and vector signal generators requiring ultra-low phase noise and wide tuning range. IC Role / Device Role / Timing Role: Primary synthesizer delivering 0.5–2.5GHz outputs with <0.17° RMS integrated phase noise (100Hz–40MHz); REFO output clocks auxiliary DACs/ADCs. Use Value: –274dBc/Hz normalized 1/f noise ensures minimal close-in jitter; SPI interface enables automated calibration scripts via PC host. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar integer-N PLL synthesizer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| HMC830LP6GE | Wider VCO range (2.2–12.4GHz), but higher normalized in-band phase noise (–219dBc/Hz); requires external VCO and loop filter components. | Supports Ka-band applications beyond LTC6946IUFD-2#PBF's 4.91GHz limit; less suitable for space-constrained base station cards due to external component count. | Select HMC830LP6GE when extending beyond 4.91GHz or needing higher output power; prefer LTC6946IUFD-2#PBF for integrated, low-noise 3–5GHz solutions with minimal layout area. |
| ADF4355BCPZ | Fractional-N architecture with 135MHz PFD max; integrated VCO (3.4–6.8GHz); –223dBc/Hz normalized in-band phase noise; larger 32-lead LFCSP package. | Better fractional resolution for fine frequency steps; wider VCO coverage overlaps LTC6946IUFD-2#PBF's band but adds complexity in loop filter design. | Choose ADF4355BCPZ for applications requiring sub-Hz frequency resolution or multi-band coverage up to 6.8GHz; LTC6946IUFD-2#PBF remains optimal for pure integer-N, lowest-noise 3.08–4.91GHz synthesis. |
Compared with HMC830LP6GE and ADF4355BCPZ, the LTC6946IUFD-2#PBF delivers superior in-band phase noise (–226dBc/Hz) in its designated band, eliminates external VCO components, and fits into a smaller 4mm × 5mm footprint - making it the preferred choice for high-density, noise-critical wireless infrastructure designs where integer-N performance suffices.
Availability
LTC6946IUFD-2#PBF is available at Aetrix Electronics and suitable for wireless infrastructure, military radio, and test equipment applications requiring stable component supply, long-term lifecycle support, and guaranteed performance across –40°C to 105°C.
Supply support for LTC6946IUFD-2#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its high-performance analog IC portfolio, including precision timing, RF, and power management products for demanding industrial and communications markets.
The LTC6946 product line delivers ultralow-noise, fully integrated PLL synthesizers targeting wireless base stations, secure radios, and instrumentation - emphasizing phase noise performance, integration density, and robust operation in harsh thermal environments.
FAQ
What is the guaranteed VCO frequency range for the LTC6946IUFD-2#PBF?
The LTC6946IUFD-2#PBF is the LTC6946-2 variant, with a guaranteed VCO frequency range of 3.08GHz to 4.91GHz. This range is factory-characterized and specified over the full –40°C to 105°C operating temperature range. Output frequencies from 0.513GHz to 2.455GHz are achieved using the internal 1–6 output divider, as confirmed in the "Available Options" table of the datasheet.
Does the LTC6946IUFD-2#PBF require external VCO components?
No, the LTC6946IUFD-2#PBF does not require external VCO components. It integrates a fully self-contained VCO core with internal calibration circuitry that automatically adjusts tuning voltage post-power-up to achieve the target frequency. No external inductors, varactors, or resonators are needed - only the external loop filter (R, C) between CP and TUNE pins is required for PLL operation.
How is the RF output configured on the LTC6946IUFD-2#PBF?
The LTC6946IUFD-2#PBF provides differential RF output on pins RF+ and RF–, each with a 136Ω internal pull-up to VRF+. For single-ended use, one pin is terminated to 50Ω while the other drives the load; for differential use, both pins connect to a balun or differential receiver. Output frequency is set by the VCO frequency divided by O (1–6), and output power ranges from –9.7dBm to 2.3dBm depending on O and RFO[1:0] register setting.
What supply voltages does the LTC6946IUFD-2#PBF require?
The LTC6946IUFD-2#PBF requires two distinct supply domains: 3.3V (±150mV) for VREF+, VREFO+, VD+, and VRF+ pins, and 5.0V (±250mV) for VVCO+ and VCP+ pins. These rails must be independently bypassed - 0.1µF ceramics near VREF+/VD+/VCP+, 0.01µF + 1µF ceramics near VVCO+, and 0.01µF near VRF+. Mixing or sharing these supplies degrades phase noise and may cause functional failure.
Can the LTC6946IUFD-2#PBF be used with a 100MHz reference input?
Yes, the LTC6946IUFD-2#PBF supports reference input frequencies from 10MHz to 250MHz, including 100MHz. The REF+/REF– inputs are high-impedance differential, self-biased, and require 1µF AC-coupling capacitors. For 100MHz operation, the FILT[1:0] bits should be set to '0' per Table 1, and BST should be set to '0' since VREF ≥2.0VP-P is expected - ensuring optimal reference buffer linearity and noise performance.
LTC6946IUFD-2#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Clock/Frequency Synthesizer (RF/IF), Integer N
- PLL:
- Yes
- Input:
- Clock
- Output:
- Clock
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 1:1
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 4.91GHz
- Divider/Multiplier:
- Yes/Yes
- Voltage - Supply:
- 3.15V ~ 5.25V
- Operating Temperature:
- -40°C ~ 105°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 28-QFN (4x5)
LTC6946IUFD-2#PBF FAQ
1.How can I place an order for LTC6946IUFD-2#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC6946IUFD-2#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC6946IUFD-2#PBF reliable?
The price and inventory of LTC6946IUFD-2#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC6946IUFD-2#PBF is usually 5 days.
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We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC6946IUFD-2#PBF transactions.
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LTC6946IUFD-2#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC6946IUFD-2#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC6946IUFD-2#PBF?
For technical support, including LTC6946IUFD-2#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC6946IUFD-2#PBF requirements.
6.How does Aetrix verify that LTC6946IUFD-2#PBF is sourced from the original manufacturer or authorized distributors?
All LTC6946IUFD-2#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC6946IUFD-2#PBF meets industry standards.
7.What is the process for return or replacement of LTC6946IUFD-2#PBF?
All LTC6946IUFD-2#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC6946IUFD-2#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC6946IUFD-2#PBF part is unused and in its original packaging.
Return procedure for LTC6946IUFD-2#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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