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Analog Devices Inc. LTC6946IUFD-2#TRPBF
- Part No.:
- LTC6946IUFD-2#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 28-WFQFN Exposed Pad
- Datasheet:
-
LTC6946IUFD-2#TRPBF.pdf
- Description:
- IC CLK/FREQ SYNTH 28QFN
- Quantity:
- Payment:
- Shipping:
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Product details
Overview
LTC6946IUFD-2#TRPBF from Analog Devices (formerly Linear Technology) is an ultralow-noise integer-N PLL synthesizer with integrated VCO, operating across 3.08GHz to 4.91GHz (VCO range) and delivering RF output from 0.513GHz to 4.91GHz via programmable 1–6 output divider. It features –226dBc/Hz normalized in-band phase noise floor, 11.2mA adjustable charge pump current, and SPI-controlled configuration - used in LTE/W-CDMA base station local oscillators and test equipment LO generation.
For engineers reviewing the LTC6946IUFD-2#TRPBF datasheet, LTC6946IUFD-2#TRPBF pinout, LTC6946IUFD-2#TRPBF application, or LTC6946IUFD-2#TRPBF equivalent, this page delivers verified package mapping (28-lead 4mm × 5mm QFN), validated pin functions, confirmed frequency coverage per variant, real-world phase noise performance at 10kHz/1MHz offsets, and two rigorously cross-checked alternative synthesizers for RF system design.
Technical Context
The LTC6946IUFD-2#TRPBF implements a fully integrated PLL architecture with reference divider (1–1023), phase-frequency detector (PFD), ultralow-noise charge pump (250µA–11.2mA), integer feedback divider (32–65535), and on-die VCO calibrated without external components. Its VCO tuning sensitivity is 4.7–7.0%Hz/V over the 3.08–4.91GHz range, and it supports configurable lock window width (3–90ns) and status reporting via STAT pin or SPI register.
It uses differential REF± inputs (10–250MHz, 0.5–2.7VP-P), provides buffered REFO output (≤250MHz), and drives differential RF± outputs with 50% duty cycle, 136Ω pull-up, and mute capability (<170ns disable time). All supply domains are segregated: 3.3V for digital/reference/RF sections, 5V for VCO and charge pump.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCO Frequency Range | 3.08GHz to 4.91GHz - defines usable LO band for LTE Band 7/38/41 and W-CDMA uplink/downlink synthesis. |
| RF Output Frequency Range | 0.513GHz to 4.91GHz - achieved via O_DIV = 1–6, enabling flexible IF/RF translation in wideband receivers. |
| Normalized In-Band Phase Noise Floor | –226dBc/Hz - enables <0.17° RMS integrated jitter (100Hz–40MHz), critical for high-order QAM constellations. |
| Charge Pump Current Range | 250µA to 11.2mA - allows loop filter optimization for stability vs. settling time trade-offs in different bandwidths. |
| Reference Input Frequency | 10MHz to 250MHz - supports crystal oscillator, TCXO, or clock generator inputs without external conditioning. |
| Output Divider | Integer 1–6 with 50% duty cycle - ensures clean square-wave LO for mixers requiring precise edge timing. |
| Supply Voltages | 3.3V (VREF+/VREFO+/VD+/VRF+), 5V (VVCO+/VCP+) - mandates dual-rail PCB layout with independent decoupling. |
Pinout & Package
Package: 28-lead (4mm × 5mm) plastic QFN (UFD), exposed pad (Pin 29) soldered to ground plane for thermal and electrical integrity. Operating junction temperature: –40°C to +105°C.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VREFO+ (1) | REFO buffer supply | 3.3V rail dedicated to low-noise reference output; requires local 0.1µF bypass to GND. |
| REFO (2) | Buffered reference output | AC-coupled square wave (≤250MHz); self-biased, needs 22nF series capacitor. |
| STAT (3) | Status indicator | Programmable OR of LOCK/UNLOCK/ALC flags; open-drain CMOS output. |
| CS (4) | SPI chip select | Active-low enable for serial interface; must meet tCSS ≥10ns setup before SCLK. |
| SCLK (5) | SPI clock | CMOS input; min 25ns high/low time; data latched on rising edge. |
| SDI (6) | SPI data input | CMOS input; data valid 6ns before SCLK rising edge (tCS). |
| SDO (7) | SPI data output | Three-state CMOS; data valid 16ns after SCLK rising edge (tDO). |
| VD+ (8) | Digital core supply | 3.3V rail for SPI logic and control registers; local 0.1µF bypass required. |
| MUTE (9) | RF output disable | Active-low CMOS input; mutes RF± within 110ns, preserving bias for fast re-enable. |
| GND (10,17,21,23,29) | Ground return | Multiple dedicated GND pins + exposed pad; all require low-inductance vias to solid ground plane. |
| RF– / RF+ (11,12) | Differential RF output | Open-collector with internal 136Ω pull-ups to VRF+; single-ended use requires 50Ω termination on unused pin. |
| VRF+ (13) | RF output supply | 3.3V rail for RF buffer; bypassed with 0.01µF ceramic capacitor close to pin. |
| BB (14) | RF reference bypass | Must connect 1.0µF capacitor directly to GND; no signal coupling allowed. |
| TUNE (15) | VCO tuning voltage input | Analog input for loop filter connection; sensitive to noise - route away from digital traces. |
| TB (16) | VCO bypass node | Connects to CMA/CMB/CMC; bypassed with 2.2µF capacitor - critical for phase noise performance. |
| CMC/CMB/CMA (18–20) | VCO bias inputs | Internally tied to TB; short trace routing and shared 2.2µF bypass essential for low VCO noise. |
| VVCO+ (22) | VCO core supply | 5V rail; requires both 0.01µF and 1µF ceramics in parallel near pin. |
| VCP+ (24) | Charge pump supply | 5V rail; bypassed with 0.1µF ceramic; separate from VVCO+ for optimal PSRR. |
| CP (25) | Charge pump output | Bidirectional current source/sink; connects to loop filter integrator node. |
| VREF+ (26) | Reference input supply | 3.3V rail for REF± buffer; local 0.1µF bypass mandatory. |
| REF– / REF+ (27,28) | Differential reference input | High-Z, self-biased inputs; require 1µF AC-coupling; single-ended use grounds REF–. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated VCO with auto-calibration | Eliminates external tank components and factory calibration; achieves target frequency within ±0.1% after power-on reset. |
| Programmable output divider (1–6) | Enables single device to serve multiple IF bands (e.g., 1.54GHz for LTE Band 3, 3.08GHz for Band 41) without redesign. |
| Configurable charge pump clamps | VCLMP(LO) = 0.84V and VCLMP(HI) = –0.96V (vs VCP+) allow safe VCO monitoring without external level-shifting circuitry. |
| SPI-compatible serial interface | Supports full register read/write, status polling, and dynamic reconfiguration - essential for adaptive radio architectures. |
| Low-noise reference buffer (REFO) | Delivers –155dBc/Hz phase noise at 10MHz, enabling clean local oscillator injection in heterodyne receivers. |
| Mute function with sub-200ns response | Allows rapid RF blanking during TDD switching or burst-mode operation without disrupting PLL lock state. |
Applications
| Wireless Base Station LO | Broadband Test Equipment |
|---|---|
|
Use Scenario: Generating stable local oscillator signals for LTE FDD/TDD transceivers operating in Bands 7, 38, and 41. IC Role / Device Role / Timing Role: Integer-N PLL synthesizer providing 3.08–4.91GHz VCO output, divided down to 1.54–2.455GHz for mixer drive. Use Value: –226dBc/Hz normalized in-band phase noise ensures EVM <2.5% for 256-QAM, meeting 3GPP TS 36.104 spectral mask requirements. |
Use Scenario: Programmable LO source in vector signal analyzers and RF signal generators covering 500MHz–5GHz. IC Role / Device Role / Timing Role: High-stability frequency synthesizer with SPI reprogramming for rapid sweep and channel hopping. Use Value: 11.2mA charge pump current and 40kHz loop bandwidth support <100µs frequency settling for automated test sequences. |
| Military Secure Radio | 5G NR FR1 Transceiver |
|
Use Scenario: Low-probability-of-intercept (LPI) waveform synthesis requiring ultra-low spurious emissions. IC Role / Device Role / Timing Role: Primary frequency source with –103dBc worst-case spurious (fPFD offset) and <–157dBc/Hz wideband noise floor. Use Value: Integrated VCO eliminates external varactor drift, ensuring long-term frequency stability under thermal stress (–40°C to +105°C). |
Use Scenario: Dual-LO architecture for 5G NR sub-6GHz transceivers supporting 100MHz channel bandwidths. IC Role / Device Role / Timing Role: Synthesizer generating 3.84–4.91GHz VCO output, divided by 2 or 3 to produce 1.92–2.455GHz and 1.28–1.637GHz LOs. Use Value: O_DIV = 1–6 with 50% duty cycle ensures precise edge alignment for I/Q modulator clocks, minimizing quadrature error. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar integer-N PLL synthesizer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| HMC830LP6GE | Wider VCO range (2.2–12.4GHz), but higher normalized in-band phase noise (–214dBc/Hz) and no integrated REFO buffer. | Preferred for multi-band test equipment needing >6GHz coverage; less suitable for space-constrained base station cards requiring low-noise reference distribution. | Select when extended frequency range outweighs need for ultra-low phase noise and integrated reference buffering. |
| ADF4355BCPZ | Fractional-N architecture, lower max VCO frequency (4.4GHz), –223dBc/Hz normalized phase noise, and integrated LDOs reduce external component count. | Better for systems requiring fine frequency resolution (sub-Hz) and simplified power delivery; not drop-in due to different register map and SPI timing. | Choose for applications demanding fractional frequency steps or reduced BOM count, accepting slightly higher in-band noise than LTC6946IUFD-2#TRPBF. |
Compared with HMC830LP6GE and ADF4355BCPZ, the LTC6946IUFD-2#TRPBF delivers superior in-band phase noise and integrated REFO buffering - making it optimal for high-order modulation schemes in thermally constrained wireless infrastructure, while the alternatives trade noise performance for broader frequency coverage or fractional resolution.
Availability
LTC6946IUFD-2#TRPBF is available at Aetrix Electronics and suitable for wireless infrastructure, test and measurement instrumentation, and secure communications systems requiring stable component supply, full production traceability, and guaranteed long-term availability.
Supply support for LTC6946IUFD-2#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its high-performance analog IC portfolio, focusing on precision signal processing, RF, and power management solutions for demanding industrial and communications markets.
The LTC6946IUFD-2#TRPBF belongs to Linear's ultralow-noise RF synthesizer product line, designed specifically for cellular base stations, military radios, and high-end test equipment where phase noise, spurious suppression, and integration density are critical.
FAQ
What is the VCO frequency range supported by the LTC6946IUFD-2#TRPBF?
The LTC6946IUFD-2#TRPBF supports a VCO frequency range of 3.08GHz to 4.91GHz, as specified in the "Available Options" table and confirmed in the Electrical Characteristics section (fVCO parameter, LTC6946-2 variant). This range is fixed per part number and cannot be extended beyond these limits by programming or external components.
Does the LTC6946IUFD-2#TRPBF support fractional-N synthesis?
No, the LTC6946IUFD-2#TRPBF is strictly an integer-N PLL synthesizer. Its feedback divider (N_DIV) accepts only integer values from 32 to 65535, and the device lacks delta-sigma modulators or fractional accumulators required for fractional-N operation. All frequency resolution is determined by the reference input and integer division ratios.
How is the output frequency calculated for the LTC6946IUFD-2#TRPBF?
The output frequency of the LTC6946IUFD-2#TRPBF is calculated as fRF = fVCO / O_DIV, where fVCO is the selected VCO frequency (3.08–4.91GHz) and O_DIV is the programmable output divider value (1–6). For example, with fVCO = 4.0GHz and O_DIV = 4, fRF = 1.0GHz - a value confirmed in the "Output Frequency Range vs Output Divider Setting" table for LTC6946IUFD-2.
What is the purpose of the TB, CMA, CMB, and CMC pins on the LTC6946IUFD-2#TRPBF?
TB (Pin 16) is the VCO bypass node, internally connected to CMA, CMB, and CMC (Pins 18–20). These pins form the VCO bias network and must be tied together with a short trace and bypassed to GND using a single 2.2µF ceramic capacitor. This configuration stabilizes VCO core bias and is critical to achieving the specified –226dBc/Hz normalized phase noise floor.
Can the LTC6946IUFD-2#TRPBF be used with a single-ended reference input?
Yes, the LTC6946IUFD-2#TRPBF supports single-ended reference inputs: apply the signal to REF+ (Pin 28) and bypass REF– (Pin 27) to GND with a 1µF capacitor for signals ≤2.7VP-P, or with a 47pF capacitor for larger amplitudes. This configuration is explicitly documented in the "Reference Input Buffer" section and Figure 1 of the datasheet.
LTC6946IUFD-2#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Clock/Frequency Synthesizer (RF/IF), Integer N
- PLL:
- Yes
- Input:
- Clock
- Output:
- Clock
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 1:1
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 4.91GHz
- Divider/Multiplier:
- Yes/Yes
- Voltage - Supply:
- 3.15V ~ 5.25V
- Operating Temperature:
- -40°C ~ 105°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 28-QFN (4x5)
LTC6946IUFD-2#TRPBF FAQ
1.How can I place an order for LTC6946IUFD-2#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC6946IUFD-2#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC6946IUFD-2#TRPBF reliable?
The price and inventory of LTC6946IUFD-2#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC6946IUFD-2#TRPBF is usually 5 days.
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We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC6946IUFD-2#TRPBF transactions.
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LTC6946IUFD-2#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC6946IUFD-2#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC6946IUFD-2#TRPBF?
For technical support, including LTC6946IUFD-2#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC6946IUFD-2#TRPBF requirements.
6.How does Aetrix verify that LTC6946IUFD-2#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC6946IUFD-2#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC6946IUFD-2#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC6946IUFD-2#TRPBF?
All LTC6946IUFD-2#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC6946IUFD-2#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC6946IUFD-2#TRPBF part is unused and in its original packaging.
Return procedure for LTC6946IUFD-2#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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