My Inquiry
My Account
Analog Devices Inc. LTC6946IUFD-3#TRPBF
- Part No.:
- LTC6946IUFD-3#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 28-WFQFN Exposed Pad
- Datasheet:
-
LTC6946IUFD-3#TRPBF.pdf
- Description:
- IC CLK/FREQ SYNTH 28QFN
- Quantity:
- Payment:
- Shipping:
Inventory:4,771
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC6946IUFD-3#TRPBF from Analog Devices (formerly Linear Technology) is an ultralow-noise integer-N PLL synthesizer with integrated VCO, operating across 3.84–5.79 GHz (VCO), delivering RF output from 0.64–5.79 GHz via programmable 1–6 divider. It features –226 dBc/Hz normalized in-band phase noise floor, 11.2 mA adjustable charge pump current, and SPI-controlled configuration - used in LTE/W-CDMA base station local oscillators and broadband test equipment.
For engineers reviewing the LTC6946IUFD-3#TRPBF datasheet, LTC6946IUFD-3#TRPBF pinout, LTC6946IUFD-3#TRPBF application, or LTC6946IUFD-3#TRPBF equivalent, this page provides verified package mapping (28-lead 4mm × 5mm QFN), confirmed VCO tuning sensitivity (4.0–6.0 %Hz/V), validated RF output power range (–9.7 to 2.3 dBm, single-ended), and two field-validated alternative parts for frequency-agile RF subsystem design.
Technical Context
The LTC6946IUFD-3#TRPBF implements a fully integrated PLL architecture with reference divider (1–1023), phase-frequency detector, ultralow-noise charge pump (250 µA–11.2 mA), integer feedback divider (32–65535), and on-die VCO calibrated without external components. Its output divider supports six integer ratios (1–6) with 50% duty cycle and buffered RF± differential outputs.
It uses dual supply domains: 3.3 V for digital/reference/RF circuitry (VREF+, VREFO+, VD+, VRF+) and 5 V for VCO/charge pump (VVCO+, VCP+). The TUNE pin accepts 1.60–2.85 V control voltage; status reporting is configurable via STAT pin and SPI-accessible register; lock detection window is programmable (3–90 ns).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCO Frequency Range | 3.84–5.79 GHz - defines usable LO band for 5G FR1/WiMAX uplink/downlink synthesis. |
| RF Output Frequency Range | 0.64–5.79 GHz - achieved via O_DIV = 1–6; enables flexible IF/RF translation without external dividers. |
| Normalized In-Band Phase Noise Floor | –226 dBc/Hz - sets fundamental limit on close-in jitter; critical for EVM-sensitive 256-QAM systems. |
| Charge Pump Current Range | 250 µA to 11.2 mA - allows loop filter optimization across bandwidths (25–123 kHz) and PFD frequencies. |
| Reference Input Frequency | 10–250 MHz - supports crystal, TCXO, or clock generator inputs; enables fractional-equivalent resolution via high-R division. |
| Output Divider Range | 1 through 6 - provides exact harmonic suppression and 50% duty cycle for balanced mixer drive. |
| Supply Voltages | 3.3 V (digital/reference/RF), 5 V (VCO/charge pump) - mandates dual-rail PCB layout with separate low-noise LDOs. |
Pinout & Package
Package: 28-lead (4 mm × 5 mm) plastic QFN (UFD), exposed pad (Pin 29) soldered to ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VREFO+ (1) | REFO buffer supply | 3.3 V rail for low-noise reference output; requires 0.1 µF local bypass to GND. |
| REFO (2) | Reference output | Buffered square wave (≤250 MHz); AC-coupled via 22 nF; self-biased for 50 Ω drive. |
| STAT (3) | Status indicator | Configurable OR of LOCK/UNLOCK/ALC flags; enables real-time PLL health monitoring. |
| CS (4) | SPI chip select | Active-low enable for serial register access; must meet tCSS ≥ 10 ns setup timing. |
| SCLK (5) | SPI clock | Rising-edge sampled; min 25 ns high/low time; supports up to 10 MHz operation. |
| SDI (6) | SPI data input | CMOS input for register writes; requires tCS ≥ 6 ns setup/hold relative to SCLK. |
| SDO (7) | SPI data output | Three-state CMOS output; valid tDO ≤ 16 ns after SCLK edge; Hi-Z leakage ±1 µA. |
| VD+ (8) | Digital supply | 3.3 V for SPI logic; bypassed with 0.1 µF ceramic capacitor near pin. |
| MUTE (9) | RF output disable | Active-low; mutes RF± within 110 ns; preserves internal bias for fast re-enable. |
| GND (10,17,21,23,29) | Ground return | Multiple dedicated GND pins + exposed pad; require low-inductance vias to inner ground plane. |
| RF– / RF+ (11,12) | Differential RF output | Open-collector with 136 Ω pull-ups to VRF+; single-ended use requires 50 Ω termination on unused pin. |
| VRF+ (13) | RF output supply | 3.3 V for RF buffer; bypassed with 0.01 µF ceramic capacitor; decouples high-frequency noise. |
| BB (14) | RF reference bypass | Must connect 1.0 µF capacitor to GND; no signal coupling permitted. |
| TUNE (15) | VCO control voltage | Accepts 1.60–2.85 V analog tuning input; connects to loop filter output; sensitive to noise. |
| TB (16) | VCO bypass | Connects to CMA/CMB/CMC; bypassed with 2.2 µF capacitor; critical for VCO phase noise. |
| CMC/CMB/CMA (18–20) | VCO bias inputs | Internally tied to TB; short trace routing required; avoid routing under package for best noise performance. |
| VVCO+ (22) | VCO core supply | 5 V rail; bypassed with 0.01 µF + 1 µF ceramics; low-noise regulation essential for VCO stability. |
| VCP+ (24) | Charge pump supply | 5 V rail; bypassed with 0.1 µF ceramic; separates charge pump noise from VCO supply. |
| CP (25) | Charge pump output | Bidirectional current source/sink; connects directly to loop filter; sensitive to parasitic capacitance. |
| VREF+ (26) | Reference input supply | 3.3 V for REF± buffer; bypassed with 0.1 µF ceramic; ensures stable input biasing. |
| REF– / REF+ (27,28) | Differential reference input | High-Z, self-biased; require 1 µF AC coupling; single-ended use needs REF– bypassed to GND. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated VCO calibration | Eliminates factory trimming or system-level VCO calibration; achieves target fVCO within ±0.5% after power-on reset. |
| Programmable output divider (1–6) | Enables exact frequency synthesis without external dividers; maintains 50% duty cycle for mixer LO drive. |
| Configurable lock detection window | Four settings (3/10/30/90 ns) allow trade-off between false-lock immunity and lock acquisition speed. |
| Low-noise reference buffer | –155 dBc/Hz phase noise at 10 MHz enables clean reference injection into cascaded PLL stages. |
| Charge pump voltage clamps | Selectable high/low clamps (VCLMP(HI)/VCLMP(LO)) support VCO monitoring and loop filter diagnostics. |
| SPI-compatible serial interface | Full read/write access to all registers including STATUS, R_DIV, N_DIV, O_DIV, and FILT/BST bits. |
Applications
| Wireless Base Station LO | Broadband Test Equipment |
|---|---|
Use Scenario: Generating local oscillator signals for LTE FDD/TDD and W-CDMA transceivers operating in 1.8–2.2 GHz and 2.5–2.7 GHz bands. IC Role / Device Role / Timing Role: Integer-N PLL synthesizer providing low-jitter, spurious-free LO with fast frequency hopping (240 MHz step in 35 µs). Use Value: Achieves <–103 dBc spurious and 0.17° RMS integrated phase noise (100 Hz–40 MHz), meeting 3GPP ACLR and EVM requirements. |
Use Scenario: Frequency synthesis in vector signal analyzers and arbitrary waveform generators requiring wideband, low-phase-noise outputs. IC Role / Device Role / Timing Role: Core RF synthesizer generating tunable 0.64–5.79 GHz outputs with programmable divide-by-N for harmonic rejection. Use Value: Delivers –226 dBc/Hz normalized in-band phase noise floor and –155 dBc/Hz wideband floor, enabling sub-0.1% EVM at 64-QAM. |
| Military Secure Radio | 5G NR FR1 Infrastructure |
Use Scenario: Low-probability-of-intercept (LPI) waveform generation in tactical radios using frequency-hopping spread spectrum (FHSS) across UHF/SHF bands. IC Role / Device Role / Timing Role: High-stability, low-spur synthesizer supporting rapid hop-set switching with deterministic lock timing. Use Value: Lock window hysteresis (22%) prevents false unlocks during transient conditions; mute enable/disable times (110/170 ns) minimize spectral leakage during hops. |
Use Scenario: Massive MIMO active antenna unit (AAU) LO distribution where phase coherence across 64+ elements is mandatory. IC Role / Device Role / Timing Role: Reference-grade PLL providing synchronized, low-jitter clocks to multiple RFICs via daisy-chained SPI and common REF input. Use Value: Integrated 1/f noise of –274 dBc/Hz enables <100 fs RMS jitter at 100 kHz offset, preserving beamforming accuracy. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar integer-N PLL synthesizer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| HMC830LP6GE | Wider VCO range (2.2–10.5 GHz), higher max PFD frequency (100 MHz), but higher normalized in-band phase noise (–219 dBc/Hz). | Preferred for multi-band test equipment needing >6 GHz coverage; less suitable for EVM-critical 5G FR1 where –226 dBc/Hz is required. | Select HMC830LP6GE when extending beyond 5.79 GHz or requiring >25 MHz PFD; verify loop filter redesign for higher charge pump gain. |
| ADF4371BCPZ | Fractional-N architecture, integrated LDOs, lower power (220 mA vs 390 mA), but wider in-band phase noise floor (–220 dBc/Hz) and no integrated VCO calibration. | Better for battery-powered portable analyzers; unsuitable for production base stations requiring zero-calibration manufacturing flow. | Choose ADF4371BCPZ for portable instrumentation with tight power budgets; accept added calibration complexity for fractional resolution. |
Compared with HMC830LP6GE and ADF4371BCPZ, the LTC6946IUFD-3#TRPBF delivers superior in-band phase noise and factory-calibrated VCO operation - making it optimal for high-EVM infrastructure where deterministic performance and minimal system-level calibration are mandatory.
Availability
LTC6946IUFD-3#TRPBF is available at Aetrix Electronics and suitable for wireless infrastructure, test equipment, and secure communications systems requiring stable component supply, long-term lifecycle assurance, and full traceability.
Supply support for LTC6946IUFD-3#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and RF ICs, serving precision instrumentation, communications, and industrial markets.
The LTC6946IUFD-3#TRPBF belongs to Linear's ultralow-noise RF synthesis product line, designed specifically for demanding wireless infrastructure and test equipment applications where phase noise, spurious performance, and integration reduce bill-of-materials and layout complexity.
FAQ
What is the VCO frequency range supported by the LTC6946IUFD-3#TRPBF?
The LTC6946IUFD-3#TRPBF supports a VCO frequency range of 3.84 GHz to 5.79 GHz, as specified in the Absolute Maximum Ratings and Electrical Characteristics tables. This range is fixed per variant and confirmed by the "Available Options" table showing LTC6946IUFD-3 with VCO FREQUENCY RANGE (GHz) = 3.840 to 5.790. Operation outside this band is not guaranteed and may result in loss of lock or degraded phase noise.
Does the LTC6946IUFD-3#TRPBF require external VCO calibration?
No, the LTC6946IUFD-3#TRPBF does not require external VCO calibration. The device performs internal calibration after each power cycle or software power-on-reset (POR), as stated in Note 3: "Valid for 1.60V ≤ TUNE ≤ 2.85V with part calibrated after a power cycle or software power-on-reset (POR)." This eliminates factory trimming and simplifies system integration.
What is the maximum RF output power of the LTC6946IUFD-3#TRPBF and under what conditions?
The maximum RF output power of the LTC6946IUFD-3#TRPBF is 2.3 dBm (single-ended, fRF = 900 MHz, RFO[1:0] = 3, LC match), per the Electrical Characteristics table. This occurs with output divider setting O = 1 and load impedance matched to 50 Ω. Power drops to –9.7 dBm at O = 1 with RFO[1:0] = 0, confirming programmable output scaling.
How is the LTC6946IUFD-3#TRPBF's phase noise performance quantified in datasheet specifications?
The LTC6946IUFD-3#TRPBF's phase noise is quantified by three key metrics: –226 dBc/Hz normalized in-band phase noise floor (LM(NORM)), –274 dBc/Hz normalized in-band 1/f noise (LM(NORM – 1/f)), and –155 dBc/Hz wideband output phase noise floor (LM) at 40 MHz offset. These values are measured per Note 6 with fVCO = 5.0 GHz, OD[2:0] = 1, and referenced to 10 MHz PFD.
Can the LTC6946IUFD-3#TRPBF be used with a single-ended reference input?
Yes, the LTC6946IUFD-3#TRPBF supports single-ended reference input: apply the signal to REF+ and bypass REF– to GND with a 1 µF capacitor (or 47 pF if VP-P > 2.7 V), as specified in the Pin Functions section and Figure 1. The input resistance remains ~8 kΩ differential, and slew rate requirement (20 V/µs) still applies to the driven pin.
LTC6946IUFD-3#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Clock/Frequency Synthesizer (RF/IF), Integer N
- PLL:
- Yes
- Input:
- Clock
- Output:
- Clock
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 1:1
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 5.79GHz
- Divider/Multiplier:
- Yes/Yes
- Voltage - Supply:
- 3.15V ~ 5.25V
- Operating Temperature:
- -40°C ~ 105°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 28-QFN (4x5)
LTC6946IUFD-3#TRPBF FAQ
1.How can I place an order for LTC6946IUFD-3#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC6946IUFD-3#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC6946IUFD-3#TRPBF reliable?
The price and inventory of LTC6946IUFD-3#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC6946IUFD-3#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC6946IUFD-3#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC6946IUFD-3#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC6946IUFD-3#TRPBF?
LTC6946IUFD-3#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC6946IUFD-3#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC6946IUFD-3#TRPBF?
For technical support, including LTC6946IUFD-3#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC6946IUFD-3#TRPBF requirements.
6.How does Aetrix verify that LTC6946IUFD-3#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC6946IUFD-3#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC6946IUFD-3#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC6946IUFD-3#TRPBF?
All LTC6946IUFD-3#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC6946IUFD-3#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC6946IUFD-3#TRPBF part is unused and in its original packaging.
Return procedure for LTC6946IUFD-3#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC6946IUFD-3#TRPBF Tags
-
CD74HCT4046AM96
Texas Instruments
-
MC14046BDWR2G
onsemi
-
501MILFT
Renesas
-
CD74HC7046AM
Texas Instruments
-
CDCVF2505PWR
Texas Instruments
-
RC19004A100GNL#KB0
Renesas
-
SI5351A-B-GTR
Skyworks Solutions Inc.
-
CY2305SXI-1T
Infineon Technologies
-
570BILFT
Renesas
-
CDCE913PWR
Texas Instruments
-
CY2305SXI-1HT
Infineon Technologies
-
DS1086LU+T
Analog Devices Inc./Maxim Integrated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
