Analog Devices Inc. LTC694IS8#PBF
- Part No.:
- LTC694IS8#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
LTC694IS8#PBF.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC694IS8#PBF from Analog Devices (formerly Linear Technology) is an industrial-grade microprocessor supervisory circuit in 8-lead SOIC package, providing guaranteed reset assertion down to VCC = 1V, 4.65V precision voltage monitoring, 200ms typical reset active time, and integrated battery backup switching with 1µA standby current. It serves as a system-level power integrity guardian in battery-backed CMOS RAM applications for embedded controllers.
For engineers reviewing the LTC694IS8#PBF datasheet, LTC694IS8#PBF pinout, LTC694IS8#PBF application, or LTC694IS8#PBF equivalent, this device delivers deterministic reset timing, low-dropout VOUT regulation, power-fail warning via PFI/PFO, watchdog timeout control, and chip-enable gating - all critical for reliable µP startup, brownout recovery, and nonvolatile memory protection.
Technical Context
The LTC694IS8#PBF integrates a bandgap voltage reference, precision comparator C1 (40mV hysteresis), battery switchover comparator C2 (70mV power-up/50mV power-down threshold, 20mV hysteresis), and power-fail comparator C3 (1.3V internal reference). Its reset pulse generator enforces minimum 140ms active-low RESET duration after VCC crosses threshold.
It features dual-mode oscillator control (internal or external clock via OSC SEL/OSC IN), three-level WDI input supporting watchdog enable/disable via logic level or transition, and CE IN/CE OUT gating logic that forces CE OUT high during undervoltage to prevent RAM writes - all operating across –40°C to +85°C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reset Voltage Threshold | 4.65V typical; ensures µP reset activation before VCC drops below 4.75V (5% tolerance), preventing unstable operation. |
| Reset Active Time (min) | 140ms; guarantees sufficient hold time for µP and power supply stabilization during power-up or brownout recovery. |
| VOUT Dropout (IOUT = 50mA) | VCC – 0.50V min; enables low-loss CMOS RAM supply under full load, reducing heat and improving efficiency. |
| Battery Standby Current | 1µA max; minimizes auxiliary power drain during long-term battery backup of SRAM/NOVRAM. |
| Supply Current (active) | 1.5mA max; supports low-power system design without compromising supervision functionality. |
| Watchdog Timeout (long) | 1.6s typical; provides robust fault detection window for firmware hang scenarios in safety-critical systems. |
| PFI Input Threshold | 1.30V ±0.05V; allows precise early-warning power-fail detection using external resistor divider networks. |
Pinout & Package
S8 package: 8-lead plastic SOIC, 1.27mm pitch, JEDEC MS-012AC, thermal resistance θJA = 180°C/W (FR4, still air).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1: VBATT | Battery backup input | Accepts 2.0V–4.25V auxiliary supply; triggers automatic switchover to VOUT when VCC falls below VBATT −50mV. |
| 2: VCC | Main 5V supply input | Monitored for reset generation; powers internal circuitry and drives VOUT via NMOS switch (RDS(on) ≈5Ω). |
| 3: VOUT | Backed-up memory supply output | Delivers up to 50mA from VCC or VBATT; bypassed with ≥0.1µF capacitor for stability under transient loads. |
| 4: GND | Analog/digital ground reference | Common return path for all internal comparators, oscillators, and output drivers; requires low-impedance PCB connection. |
| 5: WDI | Watchdog timer input | Three-state input: high/low > timeout disables watchdog; transition resets timer; floating disables function entirely. |
| 6: VBATT | Battery backup input | Duplicate pin (shared with Pin 1); electrically tied internally - used for mechanical robustness in SOIC layout. |
| 7: PFO | Power-fail output | Active-low open-drain signal indicating PFI < 1.3V; used to trigger µP interrupt prior to RESET assertion. |
| 8: RESET | Microprocessor reset output | Active-low push-pull output; remains low down to VCC = 1V, ensuring controlled µP shutdown during deep brownout. |
Key Features
| Feature | Design Value |
|---|---|
| Guaranteed reset at VCC = 1V | Ensures µP remains held in reset even during severe brownout, eliminating undefined state or spurious execution. |
| Integrated battery switchover | Automatically routes VOUT from VCC to VBATT with 20mV hysteresis, eliminating need for external diodes or PMOS controllers. |
| Adjustable reset timing (via OSC SEL) | Enables fixed 200ms typical or user-defined reset duration using external capacitor on OSC IN, supporting custom system timing. |
| Power-fail warning with PFI/PFO | Provides programmable early-alert signal (via resistor divider) to initiate graceful shutdown before RESET activates. |
| Chip-enable gating (CE IN/CE OUT) | Forces CE OUT high during undervoltage, blocking RAM writes without requiring external logic or pull-ups. |
Applications
| Industrial Embedded Controller | Automotive Body Control Module |
|---|---|
|
Use Scenario: Microcontroller-based HVAC or lighting controller operating from vehicle battery with intermittent 12V supply dips. IC Role / Device Role / Timing Role: Supervises 5V rail derived from DC-DC converter; asserts RESET during cranking-induced brownouts; enables PFO-triggered EEPROM save before power loss. Use Value: Prevents corrupted configuration data and ensures deterministic restart after engine start, meeting ISO 16750-2 pulse 4 requirements. |
Use Scenario: Battery-backed real-time clock and event logger in door module with 3.3V/5V dual-rail supply. IC Role / Device Role / Timing Role: Monitors main 5V supply and switches VOUT to 3V coin cell during ignition-off; holds RESET low until stable 5V returns post-cranking. Use Value: Guarantees SRAM retention and RTC continuity during stop-start cycles, with <1µA battery drain in backup mode. |
| Medical Portable Monitor | Smart Energy Meter |
|
Use Scenario: Handheld patient monitor powered by Li-ion battery with USB charging; requires fail-safe memory retention during charge interruption. IC Role / Device Role / Timing Role: Provides VOUT-regulated 3.3V to backup SRAM; detects battery voltage sag via PFI; triggers WDI timeout if firmware hangs during ECG processing. Use Value: Ensures clinical data integrity across power transitions, satisfying IEC 62304 Class B software safety requirements. |
Use Scenario: Utility meter with tamper-detection EEPROM and metrology ASIC, operating from AC-derived 5V with supercapacitor backup. IC Role / Device Role / Timing Role: Uses VOUT to power NOVRAM during mains failure; generates PFO interrupt to store last valid kWh reading before RESET. Use Value: Meets ANSI C12.1 and IEC 62053-21 accuracy retention mandates during 100ms–1s outage windows. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX691ACSA+ | 8-pin SOIC, 4.65V reset threshold, 200ms reset timeout, but no integrated VOUT battery switch or PFO output. | Lacks power-fail warning and RAM backup supply; requires external PMOS + diode for battery switchover. | Choose when only basic reset supervision is needed and external components are acceptable for backup management. |
| TPS3823-46DBVR | 6-pin SOT-23, 4.63V reset threshold, 200ms delay, push-pull RESET, but no watchdog, battery backup, or PFI/PFO. | No memory protection or early power-fail signaling; limited to simple reset-only use cases. | Select for space-constrained designs where only reset assertion is required and battery backup is handled externally. |
Compared with MAX691ACSA+ and TPS3823-46DBVR, the LTC694IS8#PBF uniquely integrates VOUT battery switching, PFO-based power-fail warning, and CE OUT write-protection gating - enabling single-chip µP supervision with zero external components for RAM backup and graceful shutdown.
Availability
LTC694IS8#PBF is available at Aetrix Electronics and suitable for industrial embedded controllers, automotive body electronics, portable medical devices, and smart energy meters requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LTC694IS8#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, industrial automation, and automotive markets.
The LTC694 belongs to Linear's µP supervisory family designed specifically for robust power monitoring, battery backup, and memory protection in mission-critical embedded systems - emphasizing guaranteed low-voltage reset, low quiescent current, and integrated functional safety features.
FAQ
What is the guaranteed minimum reset assertion voltage for LTC694IS8#PBF?
The LTC694IS8#PBF guarantees RESET remains active low down to VCC = 1V, ensuring microprocessor hold during deep brownout conditions. This is achieved through dedicated low-voltage biasing of the internal comparator and reset pulse generator, independent of the 4.65V nominal reset threshold. The specification is tested and guaranteed over the full –40°C to +85°C operating range.
Does LTC694IS8#PBF support adjustable reset timeout, and how is it configured?
Yes, LTC694IS8#PBF supports adjustable reset timeout via the OSC SEL and OSC IN pins. When OSC SEL is pulled low, an external capacitor (e.g., 47pF) between OSC IN and GND sets the reset active time per the formula in the datasheet. With OSC SEL high or floating, the internal oscillator fixes reset time at 200ms typical. This flexibility allows tuning to match specific µP power-up requirements without changing firmware.
How does the battery switchover function work in LTC694IS8#PBF?
The LTC694IS8#PBF uses comparator C2 to continuously compare VCC and VBATT. When VCC rises 70mV above VBATT, VOUT connects to VCC via an NMOS switch (RDS(on) ≈5Ω). When VCC falls 50mV below VBATT, VOUT switches to VBATT through a 125Ω PMOS switch. Hysteresis prevents chatter near the switchover point, and the entire transition occurs within ~20µs.
Can LTC694IS8#PBF be used to protect EEPROM writes during power loss?
Yes, LTC694IS8#PBF supports EEPROM write protection via its CE OUT pin. When VCC drops below the reset threshold (4.65V), CE OUT is forced high regardless of CE IN state - disabling chip select or write enable on compatible EEPROMs like AT24C series. This hardware-enforced gating prevents partial writes and data corruption during brownout, eliminating reliance on software-based save routines.
What is the maximum load current supported by VOUT in LTC694IS8#PBF?
VOUT supports up to 50mA from VCC with a typical dropout of 0.25V at 50mA (VCC – 0.25V), and up to 250µA from VBATT in backup mode with 0.2V dropout. The NMOS switch is short-circuit protected and thermally limited. For loads exceeding 50mA, external PNP transistor drive via BATT ON output is recommended - as documented in Figure 2 of the LTC690/LTC694 datasheet.
LTC694IS8#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 4.65V
- Output:
- Open Drain or Open Collector
- Reset:
- Active High/Active Low
- Reset Timeout:
- 140ms Minimum
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SO
LTC694IS8#PBF FAQ
1.How can I place an order for LTC694IS8#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC694IS8#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC694IS8#PBF reliable?
The price and inventory of LTC694IS8#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC694IS8#PBF is usually 5 days.
3.What payment methods are accepted for LTC694IS8#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC694IS8#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC694IS8#PBF?
LTC694IS8#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC694IS8#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC694IS8#PBF?
For technical support, including LTC694IS8#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC694IS8#PBF requirements.
6.How does Aetrix verify that LTC694IS8#PBF is sourced from the original manufacturer or authorized distributors?
All LTC694IS8#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC694IS8#PBF meets industry standards.
7.What is the process for return or replacement of LTC694IS8#PBF?
All LTC694IS8#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC694IS8#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC694IS8#PBF part is unused and in its original packaging.
Return procedure for LTC694IS8#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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