Analog Devices Inc. LTC6952IUKG#PBF

Overview

LTC6952IUKG#PBF from Analog Devices is an ultralow-jitter, 4.5GHz JESD204B/C clock generator IC with 11 differential CML outputs, integrated integer-N PLL, and programmable coarse/fine delay per output. It delivers <6 fs_RMS additive jitter (12 kHz–20 MHz) and supports precise phase alignment for high-speed data converter timing in wireless infrastructure and test equipment.

For engineers reviewing the LTC6952IUKG#PBF datasheet, LTC6952IUKG#PBF pinout, LTC6952IUKG#PBF application, or LTC6952IUKG#PBF equivalent, key selection criteria include JESD204B/C Subclass 1 SYSREF generation capability, –229 dBc/Hz normalized in-band phase noise floor, 11-output synchronization via EZSync/ParallelSync, and operation across –40°C to 125°C junction temperature.

Technical Context

The LTC6952IUKG#PBF integrates a reference divider (R = 1–1023), phase-frequency detector with lock indicator, ultralow-noise charge pump (ICP = 0.423–11.2 mA), and integer feedback divider (N = 1–65535). Its VCO operates from 4.5 GHz with differential input and supports 100 Ω termination.

All 11 CML outputs feature independent M-divider (1–4096), digital half-cycle delay (0–4095 steps), and analog delay (0–63 steps, up to 1100 ps at ≤300 MHz). Output skew is ±10 ps (one part, even dividers) and propagation delay from REF± to OUT5 is 20 ps in RAO=1 mode.

Key Specifications

Pinout & Package

52-lead (7 mm × 8 mm) plastic QFN package with exposed thermal pad (Pin 53 = GND). Requires soldering of exposed pad to PCB ground plane with thermal vias per Analog Devices layout guidelines.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultralow-jitter clock generation applications.

Compared with LTC6952IUKG#PBF, LTC6957IUKG#PBF offers higher frequency headroom but sacrifices JESD204B/C functionality and output count, while LMK04832ISQE/NOPB provides superior input flexibility and jitter cleaning at the cost of higher additive jitter and no RAO mode-making LTC6952IUKG#PBF optimal for deterministic, multi-output JESD204C timing.

Availability

LTC6952IUKG#PBF is available at Aetrix Electronics and suitable for high-speed data converter clocking, wireless infrastructure baseband timing, and test and measurement equipment requiring stable component supply across extended temperature ranges.

Supply support for LTC6952IUKG#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, founded in 1965 and headquartered in Wilmington, MA.

The LTC6952IUKG#PBF belongs to Analog Devices' precision clock generation product line, designed specifically for JESD204B/C-compliant high-speed data converter timing in demanding RF, communications, and instrumentation applications.

FAQ

What is the maximum operating frequency of the LTC6952IUKG#PBF's VCO input?

The LTC6952IUKG#PBF supports a VCO input frequency range up to 4.5 GHz, as specified in the Electrical Characteristics table. This allows direct interfacing with high-frequency VCOs such as the Crystek CVCO55CC-4000-4000 without frequency division. Operation at 4.5 GHz enables generation of full-rate sampling clocks for next-generation RF data converters. The LTC6952IUKG#PBF maintains its ultralow jitter performance across this entire band.

Does the LTC6952IUKG#PBF support JESD204C as well as JESD204B?

Yes, the LTC6952IUKG#PBF explicitly supports both JESD204B and JESD204C Subclass 1 timing requirements, as confirmed in the device description and typical application diagrams. Its eleven outputs can be configured as up to five device clock/SYSREF pairs compliant with either standard. The LTC6952IUKG#PBF achieves the tight skew and deterministic latency required by JESD204C through RAO mode and EZSync/ParallelSync protocols-verified in Analog Devices' JESD204C design examples.

How does the RAO (Reference Aligned Output) mode affect propagation delay in the LTC6952IUKG#PBF?

In RAO = 1 mode, the LTC6952IUKG#PBF reduces propagation delay from REF± to OUT5 to just 20 ps (typical), compared to 450 ps in standard mode. This is achieved by bypassing the PLL path and routing the reference directly to the output divider chain. The LTC6952IUKG#PBF uses this mode to generate ultra-low-latency SYSREF signals synchronized to the reference edge-critical for time-of-flight measurements and coherent beamforming. Temperature drift is only 0.2 ps/°C in RAO mode.

What is the purpose of the EZS_SRQ pins on the LTC6952IUKG#PBF?

The EZS_SRQ+ and EZS_SRQ– pins on the LTC6952IUKG#PBF serve as synchronization request inputs that trigger deterministic SYSREF generation and multichip alignment events. When asserted, they initiate EZSync or ParallelSync protocols to align all 11 outputs across multiple LTC6952IUKG#PBF devices within <10 µs. The LTC6952IUKG#PBF accepts both CMOS and differential signaling on these pins, with 200 mV hysteresis to reject noise in high-density PCB environments.

Can the LTC6952IUKG#PBF operate with a single-ended reference input?

Yes, the LTC6952IUKG#PBF accepts single-ended reference inputs on REF+ with REF– tied to a 1.8 V bias (within 1.65–2.25 V range), as documented in the Electrical Characteristics table. Minimum detectable signal is 350 mV_P-P at 10 MHz. However, differential operation is recommended for best noise immunity and jitter performance. The LTC6952IUKG#PBF's internal self-bias circuit eliminates the need for external bias networks in single-ended configurations.