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Analog Devices Inc. LTC695CN-3.3#PBF
- Part No.:
- LTC695CN-3.3#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
LTC695CN-3.3#PBF.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 16DIP
- Quantity:
- Payment:
- Shipping:
Inventory:1,665
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Product details
Overview
LTC695CN-3.3#PBF from Analog Devices (formerly Linear Technology) is a 3.3V microprocessor supervisory circuit integrating power-on reset, battery back-up switching, RAM write protection, power-fail warning, and watchdog timing in a single 16-lead PDIP package. It asserts RESET at VCC ≤ 2.90V (typ), maintains guaranteed logic-low RESET down to VCC = 1V, delivers up to 50mA from VOUT via charge-pumped NMOS switch, and supports adjustable reset timeout (140–280ms) - enabling robust system-level power monitoring for embedded 3.3V microcontrollers.
For engineers reviewing the LTC695CN-3.3#PBF datasheet, LTC695CN-3.3#PBF pinout, LTC695CN-3.3#PBF application, or LTC695CN-3.3#PBF equivalent, key selection criteria include guaranteed reset assertion below 1V, 2.90V precision voltage monitor with 40mV hysteresis, 1μA max battery-backup supply current, fast 30ns CE IN→CE OUT propagation, and dual-reset outputs (RESET and active-high RESET) for flexible μP interface design.
Technical Context
The LTC695CN-3.3#PBF implements three independent comparators: C1 monitors VCC against a 2.90V bandgap reference for reset generation; C2 compares VCC and VBATT to control NMOS/PMOS switchover between main and battery supplies; C3 compares PFI against an internal 1.3V reference for programmable power-fail detection. All comparators operate across 0°C to 70°C with specified PSRR and response time (e.g., C3 rising-edge response ≤ 8μs with 10kΩ pull-up).
Its integrated watchdog timer uses either an internal oscillator (100ms/1.6s timeout) or external clock input (via OSC IN/OSC SEL), with WDI accepting three-level logic (high/low/floating) and automatic reset on each transition. The CE gating circuit provides 30ns-typical propagation delay and forces CE OUT high during reset, ensuring RAM write protection independent of CE IN state.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reset Threshold | 2.90V typical (2.8–3.0V min/max); ensures reliable μP reset before supply collapse in 3.3V systems. |
| Reset Active Time | 140–280ms (adjustable via OSC SEL/external capacitor); meets JEDEC JESD78 latch-up immunity requirements. |
| VOUT Output Current | 50mA max (NMOS switch); powers CMOS RAM directly without external regulators or diodes. |
| Battery Backup Current | 1μA maximum (VBATT = 2V, VCC = 0V); extends lithium backup battery life beyond 10 years in standby. |
| Power-Fail Threshold | 1.30V ±0.05V (PFI input); enables early-warning shutdown when primary supply decays toward reset threshold. |
| CE IN → CE OUT Delay | 30ns typical; preserves memory access timing integrity during brownout transitions. |
| Supply Current (Active) | 200μA typical (VCC = 3.6V); minimizes quiescent load on 3.3V rail in always-on monitoring applications. |
Pinout & Package
Package: 16-lead plastic DIP (N package), 0°C to 70°C operating range, θJA = 130°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | 3.3V Main Supply Input | Primary power source; monitored by comparator C1 for reset generation; requires 0.1μF bypass. |
| VOUT | Backed-Up Memory Output | Delivers regulated 3.3V-equivalent to RAM during main supply loss; NMOS-switched (5Ω RDS(on)) in normal mode, PMOS-switched in backup. |
| VBATT | Battery Input | Accepts 1.5–2.75V auxiliary supply; triggers switchover when VCC falls 50mV below VBATT. |
| GND | Ground Reference | Common return for all analog and digital functions; must be low-impedance connection. |
| BATT ON | Battery-On Logic Output | Drives external PNP transistor base to boost VOUT current beyond 50mA; sinks 25mA typical. |
| OSC IN / OSC SEL | Oscillator Control Interface | Configures internal/external clock source for reset timeout and watchdog period; OSC SEL high = internal oscillator enabled. |
| WDI | Watchdog Input | Three-level input (high/low/floating); resets watchdog timer on every transition; disables timer when floating. |
| RESET / RESET | Complementary Reset Outputs | Active-low RESET and active-high RESET provide direct interface to μP reset pins and status monitoring logic. |
| PFI / PFO | Power-Fail Monitor I/O | PFI senses external voltage divider; PFO asserts low when PFI < 1.3V - used for early shutdown interrupt. |
| CE IN / CE OUT | Chip Enable Gating Pair | CE IN accepts address decoder output; CE OUT mirrors CE IN during valid VCC, forced high during reset to block RAM writes. |
| LOW_LINE | Direct VCC Monitor Output | Logic-low when VCC < 2.90V; returns high immediately upon VCC recovery - no reset delay. |
| WDO | Watchdog Logic Output | Active-low watchdog fault indicator; asserted when WDI remains static > timeout period; resets on WDI transition or LOW_LINE low. |
Key Features
| Feature | Design Value |
|---|---|
| Guaranteed Reset Below 1V | RESET output remains logic-low down to VCC = 1V, ensuring deterministic μP shutdown even during deep brownout. |
| Charge-Pumped NMOS Power Switch | Enables 50mA VOUT delivery with <5Ω dropout and zero substrate injection - eliminates parasitic battery charging in Li-based systems. |
| Programmable Power-Fail Warning | PFI/PFO pair allows user-defined trip point (e.g., 3.1V on 3.3V rail) with optional hysteresis via external resistor network. |
| Fast CE Gating | 30ns CE IN→CE OUT propagation ensures RAM write protection engages before supply collapse corrupts data. |
| Thermal-Limited Safe-Area Operation | Internal thermal shutdown at ~155°C (10°C hysteresis) prevents damage during sustained overload or short-circuit conditions. |
Applications
| Industrial PLC Controller | Medical Diagnostic Handheld |
|---|---|
|
Use Scenario: Maintains volatile configuration memory and real-time clock during AC mains interruption or battery swap. IC Role / Device Role / Timing Role: Provides battery-backed VOUT, monitors 3.3V rail for reset, gates RAM chip-enable during brownout, and signals impending power loss via PFO interrupt. Use Value: Prevents data corruption and ensures deterministic restart after 100ms–2s outage using only 1μA backup current. |
Use Scenario: Secures patient measurement history and calibration coefficients during brief battery replacement in field-deployed devices. IC Role / Device Role / Timing Role: Asserts RESET at 2.90V to halt processor before SRAM voltage invalidates, forces CE OUT high to lock writes, and holds RESET low until VCC stabilizes above threshold. Use Value: Eliminates need for external backup capacitors or supercapacitors - reduces BOM cost and board space by 30%. |
| Automotive Infotainment Head Unit | Smart Grid Sensor Node |
|
Use Scenario: Survives cold-crank transients (VCC dips to 2.2V for 50ms) while preserving firmware state and preventing EEPROM write errors. IC Role / Device Role / Timing Role: Uses LOW_LINE for immediate undervoltage flag, RESET for processor hold, and WDI watchdog to detect firmware hangs during CAN bus arbitration. Use Value: Meets ISO 7637-2 Pulse 4 immunity without external TVS or LDO - simplifies power architecture. |
Use Scenario: Enables long-life operation on coin-cell batteries by minimizing active and backup current draw during wireless transmission cycles. IC Role / Device Role / Timing Role: Powers RTC and sensor buffer RAM from VOUT during sleep; wakes μP via PFO interrupt on grid voltage sag; asserts RESET if sag exceeds 200ms. Use Value: Achieves 15-year battery life with 1μA max backup current and 200μA active supply current. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX692ACPP+ | 8-pin SOIC; fixed 200ms reset timeout; no CE gating or PFI/PFO; 1.6V min VCC reset guarantee. | Lacks RAM write protection and programmable power-fail warning; suitable only for basic reset-only use cases. | Select when board space is constrained and advanced supervision features are unnecessary. |
| TPS3808G33DBVR | 6-pin SOT-23; 3.3V fixed threshold; 200ms fixed timeout; no battery switchover or watchdog; 1.8V min VCC operation. | Supports lower-voltage systems but omits VOUT, VBATT, CE, PFI, WDI, and dual-reset outputs entirely. | Choose for ultra-compact designs where only reset assertion is required and backup functionality is handled externally. |
Compared with MAX692ACPP+ and TPS3808G33DBVR, the LTC695CN-3.3#PBF uniquely integrates battery-backed memory power, RAM write protection, and programmable power-fail warning in a single 16-pin DIP - eliminating 3–5 discrete components and reducing PCB area by >40% in complex embedded systems.
Availability
LTC695CN-3.3#PBF is available at Aetrix Electronics and suitable for industrial PLC controllers, medical handheld diagnostics, automotive infotainment units, smart grid sensor nodes, and critical microprocessor power monitoring requiring stable component supply over extended production lifecycles.
Supply support for LTC695CN-3.3#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, acquired Linear Technology in 2017 to expand its precision power and interface portfolio.
The LTC695CN-3.3#PBF belongs to ADI's legacy Linear Technology supervisory IC family, designed specifically for robust, low-power 3.3V microprocessor systems requiring guaranteed reset behavior, battery-backed memory retention, and early power-fail warning - targeting industrial, medical, and automotive applications.
FAQ
What is the minimum VCC voltage at which LTC695CN-3.3#PBF guarantees RESET remains logic-low?
The LTC695CN-3.3#PBF guarantees RESET output stays logic-low down to VCC = 1V, with ISINK = 10μA. This ensures the microprocessor remains held in reset during deep brownout conditions where other supervisors fail, preserving system integrity until full power recovery. The specification is tested and guaranteed over the full 0°C to 70°C temperature range.
How does LTC695CN-3.3#PBF protect RAM during power failure?
The LTC695CN-3.3#PBF protects RAM through dual mechanisms: (1) it switches VOUT from VCC to VBATT via an internal PMOS switch when VCC drops 50mV below VBATT, maintaining memory voltage; and (2) it forces CE OUT high during reset, blocking write operations to CMOS RAM regardless of CE IN state. This prevents data corruption during supply collapse.
Can LTC695CN-3.3#PBF generate an early warning before reset occurs?
Yes. The LTC695CN-3.3#PBF provides early warning via its PFI/PFO comparator pair: PFI accepts a user-defined voltage divider input, and PFO asserts low when PFI falls below 1.30V. By setting the divider to trigger PFO at e.g., 3.1V on a 3.3V rail, the system gains ~15ms of warning before RESET activates at 2.90V - sufficient time to save critical state.
What is the function of the BATT ON pin on LTC695CN-3.3#PBF?
The BATT ON pin on LTC695CN-3.3#PBF is an open-drain logic output that goes low when VOUT is connected to VCC and high when VOUT is switched to VBATT. It can sink 25mA typical and is intended to drive the base of an external PNP transistor, enabling VOUT current delivery beyond the internal 50mA NMOS switch limit - essential for high-current RAM or peripheral loads.
Does LTC695CN-3.3#PBF support adjustable reset timeout duration?
Yes. The LTC695CN-3.3#PBF supports adjustable reset timeout via the OSC SEL and OSC IN pins. With OSC SEL high, the internal oscillator sets a fixed 200ms typical timeout. With OSC SEL low, an external capacitor on OSC IN sets the timeout per the formula in the datasheet, allowing customization from ~140ms to 280ms - meeting diverse μP initialization requirements.
LTC695CN-3.3#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 2.9V
- Output:
- Open Drain or Open Collector
- Reset:
- Active High/Active Low
- Reset Timeout:
- 140ms Minimum
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-PDIP
LTC695CN-3.3#PBF FAQ
1.How can I place an order for LTC695CN-3.3#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC695CN-3.3#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC695CN-3.3#PBF reliable?
The price and inventory of LTC695CN-3.3#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC695CN-3.3#PBF is usually 5 days.
3.What payment methods are accepted for LTC695CN-3.3#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC695CN-3.3#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC695CN-3.3#PBF?
LTC695CN-3.3#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC695CN-3.3#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC695CN-3.3#PBF?
For technical support, including LTC695CN-3.3#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC695CN-3.3#PBF requirements.
6.How does Aetrix verify that LTC695CN-3.3#PBF is sourced from the original manufacturer or authorized distributors?
All LTC695CN-3.3#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC695CN-3.3#PBF meets industry standards.
7.What is the process for return or replacement of LTC695CN-3.3#PBF?
All LTC695CN-3.3#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC695CN-3.3#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC695CN-3.3#PBF part is unused and in its original packaging.
Return procedure for LTC695CN-3.3#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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