Analog Devices Inc. LTC695CSW-3.3#PBF

Overview

LTC695CSW-3.3#PBF from Analog Devices (formerly Linear Technology) is a 3.3V microprocessor supervisory circuit integrating power-on reset, battery-backed RAM power switching, RAM write protection, power-fail warning, and watchdog timing in a single 16-pin wide SOIC package. It guarantees RESET assertion down to VCC = 1V, features a 2.90V precision reset threshold, 200ms (adjustable) reset timeout, and delivers up to 50mA from VOUT with <5Ω on-resistance. It is used in battery-powered industrial controllers and embedded systems requiring reliable low-voltage operation and data retention during main supply interruption.

For engineers reviewing the LTC695CSW-3.3#PBF datasheet, LTC695CSW-3.3#PBF pinout, LTC695CSW-3.3#PBF application, or LTC695CSW-3.3#PBF equivalent, key selection criteria include guaranteed reset at 1V VCC, 1μA max battery-backup current, fast 30ns CE gating, 2.90V reset threshold accuracy, and dual-output reset (RESET/RESET) for active-high and active-low logic interfacing.

Technical Context

The LTC695CSW-3.3#PBF implements a multi-function supervisory architecture with three independent comparators (C1 for VCC monitoring, C2 for battery switchover, C3 for PFI), an internal oscillator for adjustable reset/watchdog timing, and charge-pumped NMOS/PMOS power switches for low-dropout VOUT regulation. Its dual-mode battery switchover (70mV turn-on / 50mV turn-off threshold with 20mV hysteresis) ensures glitch-free transition between VCC and VBATT.

It integrates memory protection via CE IN/CE OUT gating with 30ns propagation delay, a user-configurable power-fail comparator (1.30V ±50mV reference), and a three-level watchdog input (WDI) supporting both internal oscillator (100ms/1.6s timeout) and external clock modes. Thermal limiting and short-circuit protection are built-in.

Key Specifications

Pinout & Package

Package: 16-lead plastic wide SO (SW), RoHS-compliant, 110°C max junction temperature, θJA = 130°C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with MAX691ACPE+ and TPS3808G33DBVR, the LTC695CSW-3.3#PBF uniquely combines 3.3V-specific reset, battery-backed VOUT delivery, CE-gated write protection, and watchdog supervision in one package - eliminating four discrete components and enabling compact, high-reliability 3.3V system supervision.

Availability

LTC695CSW-3.3#PBF is available at Aetrix Electronics and suitable for industrial PLCs, medical handhelds, automotive infotainment units, ruggedized IoT gateways, and battery-powered instrumentation requiring stable component supply and long-term lifecycle support.

Supply support for LTC695CSW-3.3#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.

The LTC695CSW-3.3#PBF belongs to Linear's legacy supervisory IC family, designed specifically for robust 3.3V microprocessor system monitoring - emphasizing ultra-low backup current, guaranteed low-VCC reset, and integrated memory protection for mission-critical embedded applications.

FAQ

What is the guaranteed minimum VCC voltage at which LTC695CSW-3.3#PBF asserts RESET?

The LTC695CSW-3.3#PBF guarantees RESET remains logic low down to VCC = 1V, ensuring the microprocessor stays in a known reset state even during severe brownout conditions. This specification is tested and guaranteed over the full operating temperature range (0°C to 70°C for the 'C' grade), and is enabled by internal level-shifting circuitry that maintains output drive capability far below the nominal 3.3V supply.

How does LTC695CSW-3.3#PBF protect RAM during power failure?

The LTC695CSW-3.3#PBF protects RAM through three coordinated mechanisms: (1) it switches VOUT from VCC to VBATT when VCC drops below VBATT −50mV, maintaining power to memory; (2) it forces CE OUT high during reset, blocking write operations to CMOS RAM; and (3) it asserts RESET/RESET to halt the μP before data corruption can occur. These functions operate autonomously without software intervention.

Can LTC695CSW-3.3#PBF be used with a 5V main supply?

No - the LTC695CSW-3.3#PBF is explicitly optimized for 3.3V systems and specifies absolute maximum VCC = 6V but functional operation only within 3.0V–5.5V per Electrical Characteristics. Its 2.90V reset threshold and internal references assume a 3.3V nominal rail; using it with 5V violates its design intent and may cause premature reset assertion or inaccurate PFI scaling. For 5V systems, use the LTC694/LTC695 (non-"-3.3") variants.

What is the purpose of the BATT ON pin on LTC695CSW-3.3#PBF?

The BATT ON pin on the LTC695CSW-3.3#PBF is an open-drain logic output that indicates when the internal PMOS battery switch is active (i.e., VOUT is sourced from VBATT). It typically sinks 25mA and is intended to drive the base of an external PNP transistor, enabling VOUT current delivery beyond the 50mA limit of the internal NMOS switch - essential for powering larger RAM arrays or peripheral ICs during backup mode.

Does LTC695CSW-3.3#PBF support adjustable reset timeout, and how is it configured?

Yes, the LTC695CSW-3.3#PBF supports adjustable reset timeout via the OSC IN and OSC SEL pins. With OSC SEL high (or floating), the internal oscillator sets a fixed 200ms timeout. With OSC SEL low, an external capacitor (e.g., 47pF) on OSC IN or an external clock signal configures custom timing - enabling precise synchronization with system boot requirements or compliance with specific safety standards.