Analog Devices Inc. LTC695CSW#PBF

Overview

LTC695CSW#PBF from Analog Devices (formerly Linear Technology) is a 16-pin microprocessor supervisory IC with integrated battery backup, power-fail warning, watchdog timer, and RAM write-protection gating. It features a 4.65V precision reset threshold, 200ms typical reset active time (adjustable), 1.6s/100ms selectable watchdog timeout, and VOUT output capable of sourcing 50mA from VCC or 250µA from VBATT. It is used in battery-backed embedded controllers requiring guaranteed reset assertion down to VCC = 1V.

For engineers reviewing the LTC695CSW#PBF datasheet, LTC695CSW#PBF pinout, LTC695CSW#PBF application, or LTC695CSW#PBF equivalent, this page delivers verified functional identity, validated 16-lead wide SOIC package mapping, confirmed dual-mode battery switchover behavior, exact reset/watchdog timing values per OSC SEL state, and two manufacturer-validated alternative parts for supervisory function replacement.

Technical Context

The LTC695CSW#PBF implements a bandgap-referenced voltage monitor (C1) with 40mV hysteresis and 10µs response time to detect VCC drop below 4.65V, forcing RESET low. Its internal oscillator-enabled when OSC SEL is high-sets fixed 200ms typical reset duration and 1.6s/100ms watchdog timeout periods; OSC SEL low enables external clock or capacitor-based timing adjustment.

Battery switchover uses comparator C2 to connect VOUT to VCC when VCC exceeds VBATT by ≥70mV (hysteresis 20mV), and to VBATT when VCC falls ≤50mV below VBATT. The charge-pumped NMOS switch (M1) delivers up to 50mA at 5Ω typical R_DS(on), while the PMOS backup switch (M2) provides 125Ω dropout path for standby operation at ≤1µA supply current.

Key Specifications

Pinout & Package

Package: 16-lead wide plastic SO (SW package), JEDEC MS-013AC, 7.5mm body width, 1.27mm pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with LTC695CSW#PBF, LTC691CSW#PBF offers identical form-factor and pin compatibility but sacrifices timing adjustability and power-fail warning, while MAX695CSA+ reduces footprint and cost at the expense of integrated battery management and memory protection features.

Availability

LTC695CSW#PBF is available at Aetrix Electronics and suitable for industrial controller power monitoring, automotive infotainment memory backup, and medical device power-fail warning requiring stable component supply across extended temperature and lifecycle planning.

Supply support for LTC695CSW#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors.

The LTC695CSW#PBF belongs to the LTC690/LTC691/LTC694/LTC695 family of microprocessor supervisory circuits, designed specifically for robust power monitoring, battery-backed memory retention, and fail-safe system recovery in embedded systems.

FAQ

What is the guaranteed minimum VCC level at which LTC695CSW#PBF asserts RESET?

LTC695CSW#PBF guarantees RESET remains logic low down to VCC = 1V, ensuring reliable microprocessor hold-down during deep brownout conditions. This specification is tested and guaranteed across temperature and process variation, independent of external pull-up strength or load, and is enabled by the internal charge-pump-assisted output stage. The LTC695CSW#PBF achieves this using a dedicated low-VCC bias network that maintains comparator and driver functionality far below standard TTL thresholds.

Can LTC695CSW#PBF be used to back up CMOS RAM without an external battery?

Yes, LTC695CSW#PBF supports capacitor-based backup via the VBATT pin. High-value capacitors (e.g., supercapacitors or large electrolytics) can be charged through VOUT and used as short-term energy sources during main power loss. The device's 1µA max standby current and 125Ω PMOS backup path minimize discharge, enabling minutes of retention for low-leakage CMOS RAM. The LTC695CSW#PBF automatically switches VOUT to VBATT when VCC drops ≤50mV below the capacitor voltage, preserving data integrity without manual intervention.

How does the watchdog timeout period change when OSC SEL is pulled low on LTC695CSW#PBF?

When OSC SEL is pulled low, LTC695CSW#PBF disables its internal oscillator and enables external timing via OSC IN. With an external clock, the watchdog timeout becomes 4032 or 960 clock cycles (long/short), introducing deterministic jitter of ±1 cycle. With an external capacitor (e.g., 47pF), nominal timeout shifts to 4kHz oscillator frequency, yielding ~250µs period resolution. The LTC695CSW#PBF's block diagram confirms the external signal passes through the same divider chain as the internal oscillator, preserving timing predictability while enabling custom intervals not available in fixed-mode operation.

What is the function of the BATT ON pin on LTC695CSW#PBF, and how is it used?

The BATT ON pin on LTC695CSW#PBF is an open-collector logic output indicating VOUT sourcing from VBATT (high) or VCC (low). It sinks up to 35mA and is commonly used to drive the base of an external PNP transistor, boosting VOUT current beyond the internal 50mA limit. During battery backup, BATT ON goes high, enabling the external switch to supply higher loads to RAM or real-time clocks. The LTC695CSW#PBF datasheet explicitly recommends this configuration in Figure 2, confirming BATT ON's role as a battery-status-controlled power-path enabler-not a general-purpose GPIO.

Does LTC695CSW#PBF provide hysteresis on its power-fail detection circuitry?

No, the PFI comparator (C3) in LTC695CSW#PBF has no internal hysteresis. However, external hysteresis can be added by connecting a resistor from PFO to PFI, creating positive feedback that establishes distinct upper (V_H) and lower (V_L) trip points. The LTC695CSW#PBF datasheet provides exact formulas for calculating R3 and R4 values based on desired hysteresis width (e.g., 850mV in Example 1). This design flexibility allows engineers to tailor noise immunity without modifying the LTC695CSW#PBF's core architecture.