Analog Devices Inc. LTC695CSW#TRPBF

Overview

LTC695CSW#TRPBF from Analog Devices (formerly Linear Technology) is a 16-pin microprocessor supervisory IC with integrated battery backup, power-fail warning, watchdog timer, and RAM write-protection gating. It features a 4.65V precision reset threshold, 200ms typical reset active time (adjustable), 1.6s/100ms selectable watchdog timeout, and VOUT output capable of sourcing 50mA from VCC or 250µA from VBATT. It is designed for critical µP power monitoring in industrial embedded systems requiring guaranteed reset assertion down to VCC = 1V.

For engineers reviewing the LTC695CSW#TRPBF datasheet, LTC695CSW#TRPBF pinout, LTC695CSW#TRPBF application, or LTC695CSW#TRPBF equivalent, key selection criteria include its dual-mode battery switchover (NMOS/PMOS), adjustable reset timing via OSC SEL/OSC IN, guaranteed low-VCC reset hold, and CE IN/CE OUT memory protection logic - all in a wide SO-16 package rated for 0°C to 70°C operation.

Technical Context

The LTC695CSW#TRPBF implements a bandgap-referenced voltage monitor (C1) for precise 4.65V reset threshold detection with 40mV hysteresis, a dedicated power-fail comparator (C3) referenced to 1.3V, and a dual-mode oscillator (internal or external clock) controlling both reset pulse width and watchdog timeout. Its charge-pumped NMOS switch (M1) delivers up to 50mA to VOUT with ~5Ω on-resistance, while a PMOS switch (M2) enables low-dropout battery backup with <125Ω resistance and 1µA standby current.

It integrates three independent comparators (C1, C2, C3), a watchdog timer with transition-triggered reset, and a chip-enable gating circuit that forces CE OUT high during undervoltage conditions. The BATT ON output provides logic-level indication of VCC/VBATT switchover state and can drive external PNP transistors for higher-current backup loads.

Key Specifications

Pinout & Package

Package: 16-lead wide plastic SO (SW), RoHS-compliant, JEDEC MS-013AC, 10.3mm × 7.5mm body, 1.27mm pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with MAX695CSA+ and TPS3808G33DBVR, the LTC695CSW#TRPBF provides uniquely integrated battery switchover, programmable timing, and hardware-enforced memory write protection - making it irreplaceable in applications demanding coordinated power, reset, and data integrity management.

Availability

LTC695CSW#TRPBF is available at Aetrix Electronics and suitable for industrial PLC controllers, medical diagnostic instruments, automotive infotainment head units, and smart energy meters requiring stable component supply with guaranteed long-term availability and traceable sourcing.

Supply support for LTC695CSW#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors.

The LTC695CSW#TRPBF belongs to the LTC690 family of microprocessor supervisory circuits, engineered specifically for robust power monitoring, battery backup, and system-level fault recovery in mission-critical embedded systems.

FAQ

What is the guaranteed minimum reset assertion voltage for LTC695CSW#TRPBF?

The LTC695CSW#TRPBF guarantees RESET remains active low down to VCC = 1V, ensuring the microprocessor stays in a known, safe state even during severe brownout conditions. This behavior is explicitly specified in the Absolute Maximum Ratings and Electrical Characteristics tables, and is a core differentiator versus standard supervisors that release reset at ~3V.

How does LTC695CSW#TRPBF handle battery switchover between VCC and VBATT?

The LTC695CSW#TRPBF uses two internal comparators (C2) to monitor the VCC–VBATT differential: it connects VOUT to VCC when VCC exceeds VBATT by ≥70mV, and switches to VBATT when VCC falls ≤50mV below VBATT. The 20mV hysteresis prevents oscillation, and the NMOS/PMOS dual-switch architecture eliminates substrate injection current that could damage lithium batteries - a key advantage over competitive solutions.

Can the reset active time of LTC695CSW#TRPBF be adjusted, and how?

Yes, the reset active time of LTC695CSW#TRPBF is adjustable via the OSC SEL and OSC IN pins. When OSC SEL is pulled low, an external clock or capacitor (e.g., 47pF to GND) on OSC IN sets the timing. With OSC SEL high or floating, the internal oscillator fixes the reset time at 200ms typical. This flexibility allows tuning to match specific µP startup requirements without external RC networks.

What is the function of CE IN and CE OUT on LTC695CSW#TRPBF, and why are they important?

CE IN accepts a chip-enable or write signal from the microprocessor, and CE OUT delivers a protected version: it follows CE IN during normal operation but is forced high whenever VCC drops below the reset threshold or VBATT is active. This unconditionally disables RAM writes during power faults, preserving data integrity without software intervention - a hardware-level safeguard critical for battery-backed memory systems.

Does LTC695CSW#TRPBF support power-fail warning, and how is it implemented?

Yes, LTC695CSW#TRPBF implements power-fail warning using the PFI (Power-Fail Input) and PFO (Power-Fail Output) pins. PFI connects to a resistor divider monitoring the supply rail; when the divided voltage falls below the internal 1.3V reference, PFO goes low - typically configured to assert 5–10ms before RESET. This gives the µP time to execute a controlled shutdown sequence and save critical data.