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Analog Devices Inc. LTC695ISW-3.3#PBF
- Part No.:
- LTC695ISW-3.3#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
LTC695ISW-3.3#PBF.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 16SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:950
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Product details
Overview
LTC695ISW-3.3#PBF from Analog Devices (formerly Linear Technology) is a 3.3V microprocessor supervisory circuit integrating power-on reset, battery back-up switching, RAM write protection, power-fail warning, and watchdog timing in a single 16-lead plastic wide SOIC package. It asserts guaranteed RESET at VCC as low as 1V, provides 2.90V precision voltage monitoring, delivers up to 50mA from VOUT with 5Ω typical on-resistance, and supports battery switchover with 70mV power-up/50mV power-down thresholds - enabling robust operation in battery-backed embedded controllers.
For engineers reviewing the LTC695ISW-3.3#PBF datasheet, LTC695ISW-3.3#PBF pinout, LTC695ISW-3.3#PBF application, or LTC695ISW-3.3#PBF equivalent, key selection criteria include guaranteed reset assertion down to 1V supply, 1μA max standby current in battery-backup mode, fast 30ns CE IN-to-CE OUT propagation delay for RAM write protection, adjustable reset active time (200ms typical, configurable via external capacitor), and thermal limiting for safe-area operation.
Technical Context
The LTC695ISW-3.3#PBF implements three independent comparators: C1 monitors VCC against a 2.90V bandgap reference with 40mV hysteresis for reset generation; C2 compares VCC and VBATT to control NMOS/PMOS power switches for seamless battery switchover; C3 compares PFI against an internal 1.3V reference to generate early power-fail warnings. All comparators operate across –40°C to +85°C.
Its integrated watchdog timer uses either an internal oscillator (100ms/1.6s timeout options) or external clock input (WDI), with timeout periods specified over temperature and exhibiting PSRR of 2–32 ms/V. The charge-pumped NMOS VOUT switch enables low-dropout operation (VCC – VOUT ≤ 0.8V at 50mA), while the PMOS battery-backup path achieves <0.1V dropout at 250μA - critical for preserving CMOS RAM data during brownouts.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reset Threshold | 2.90V typical (2.8V–3.0V min/max); ensures reliable μP reset before supply collapse into invalid logic region. |
| VOUT Output Current | 50mA max (short-circuit protected); sufficient to power multiple CMOS RAM chips without external boost. |
| Battery Standby Current | ±0.10μA max; prevents parasitic battery discharge during long-term storage or backup mode. |
| Watchdog Timeout | 100ms / 1.6s selectable; provides flexible fault-detection granularity for real-time vs. low-power applications. |
| CE IN → CE OUT Delay | 30ns typical; enables cycle-accurate write protection during supply transients without CPU intervention. |
| Supply Current (Active) | 0.6mA typical; minimizes system power budget in always-on supervisory roles. |
| RESET Low Voltage @ 1V VCC | 200mV max at 10μA sink; guarantees clean logic-low state even during deep brownout conditions. |
Pinout & Package
Package: 16-lead plastic wide SOIC (SW), 7.5mm × 10.3mm body, 1.27mm pitch, RoHS-compliant lead-free finish. Thermal resistance θJA = 130°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VBATT | Battery input | Accepts 1.5V–2.75V auxiliary supply; triggers automatic switchover when VCC drops below VBATT −50mV. |
| VOUT | Backed-up memory supply | Delivers regulated power to RAM; sourced from VCC (NMOS switch) or VBATT (PMOS switch) depending on supply hierarchy. |
| VCC | Main 3.3V supply input | Primary power source; monitored by C1 for reset generation and by C2 for switchover decisions. |
| GND | Analog/digital ground reference | Common return for all internal circuits; requires low-inductance 0.1μF bypassing at pin. |
| BATT ON | Battery-on logic output | Sinks 25mA typical; drives external PNP transistor base to extend VOUT current beyond 50mA limit. |
| LOW_LINE | VCC undervoltage indicator | Active-low open-drain output mirroring C1 comparator state; returns high immediately upon VCC recovery. |
| OSC IN | Oscillator input | Accepts external clock or capacitor (with OSC SEL low); sets watchdog/reset timing when internal oscillator disabled. |
| OSC SEL | Oscillator mode select | High/floating = internal oscillator enabled; low = external clock/capacitor mode for precise timing control. |
| RESET | Active-low μP reset | Guaranteed logic-low down to VCC = 1V; holds reset for ≥140ms after VCC recovery. |
| RESET | Active-high μP reset | Inverted copy of RESET; simplifies interface to processors requiring active-high reset assertion. |
| WDO | Watchdog logic output | Active-low signal indicating watchdog timeout; resets on every WDI transition or LOW_LINE assertion. |
| CE IN | Chip enable input | Accepts address decoder or CPU output; gated through internal logic to protect RAM writes during brownout. |
| CE OUT | Gated chip enable output | Buffered replica of CE IN above reset threshold; forced high during reset to disable RAM writes unconditionally. |
| WDI | Watchdog input | Three-level input (high/low/floating); floating disables watchdog; transitions reset timeout counter. |
| PFI | Power-fail input | Non-inverting input to C3 comparator; compared to 1.3V reference for early power-loss detection. |
| PFO | Power-fail output | Active-low open-drain output signaling PFI < 1.3V; used to trigger controlled shutdown before RESET activates. |
Key Features
| Feature | Design Value |
|---|---|
| Guaranteed reset assertion at 1V VCC | Ensures deterministic μP shutdown even during severe brownouts where other supervisors fail. |
| Charge-pumped NMOS VOUT switch | Achieves 5Ω typical on-resistance and 0.6mW typical operating power - eliminating substrate injection and battery charging artifacts seen in PNP-based competitors. |
| Adjustable reset active time | Configurable via external capacitor on OSC IN (LTC695-3.3 only); supports custom timing requirements without firmware changes. |
| Integrated RAM write protection | CE IN/CE OUT gating with 30ns propagation delay prevents partial writes during supply instability - no external logic required. |
| Thermal shutdown with hysteresis | Activates at ~155°C with ~10°C hysteresis; protects device during sustained overload or poor PCB heatsinking. |
Applications
| Industrial PLC Controller | Medical Data Logger |
|---|---|
Use Scenario: Maintains volatile configuration and runtime state in a DIN-rail mounted programmable logic controller during AC mains interruptions lasting seconds. IC Role / Device Role / Timing Role: Supervisory IC providing coordinated reset, battery-backed RAM power, and early power-fail interrupt (PFO) to initiate graceful I/O freeze and nonvolatile save. Use Value: Prevents corrupted ladder logic execution and preserves sensor calibration data using guaranteed 1V reset hold and 1μA battery standby current. | Use Scenario: Powers SRAM buffer in a portable ECG monitor during battery swap or low-battery conditions without losing waveform samples. IC Role / Device Role / Timing Role: Dual-role supervisor: VOUT supplies backed-up memory; CE OUT gates RAM writes during voltage sag detected by 2.90V threshold. Use Value: Enables hot-swap battery replacement with zero data loss via fast 30ns CE gating and seamless VBATT switchover at 50mV hysteresis. |
| Automotive Telematics Unit | Smart Energy Meter |
Use Scenario: Secures firmware state and communication buffers in a CAN-connected telematics gateway exposed to automotive load-dump and cold-crank transients. IC Role / Device Role / Timing Role: Reset generator with extended temperature range (–40°C to +85°C) and watchdog timer monitoring MCU health during CAN bus idle periods. Use Value: Eliminates spurious reboots during 12V battery dips to 6V by asserting RESET only below 2.90V with 40mV hysteresis and holding it down to 1V. | Use Scenario: Preserves tariff schedules and consumption history in a utility-grade meter during grid outages lasting hours or days. IC Role / Device Role / Timing Role: Battery management supervisor: VBATT powers VOUT in backup mode; PFI monitors regulated 3.3V rail for early warning before main supply collapse. Use Value: Extends backup runtime by 30% versus discrete solutions via 1μA max standby current and efficient PMOS backup switch (<0.1V dropout). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX691ACPE+ | 8-pin PDIP; fixed 200ms reset timeout; no CE IN/CE OUT gating; 10μA max supply current. | Lacks RAM write protection and adjustable reset timing; suitable only for basic reset-only use cases. | Select when board space is constrained and memory protection is handled externally. |
| TPS3823MPW | 6-pin SOT-23; 2.93V reset threshold; no battery switchover or PFI/PFO; 12μA supply current. | Provides only reset and watchdog functions; cannot power or protect RAM; no auxiliary supply support. | Choose for cost-sensitive, space-limited designs where battery backup is unnecessary. |
Compared with MAX691ACPE+ and TPS3823MPW, the LTC695ISW-3.3#PBF uniquely integrates battery-backed VOUT delivery, CE-gated RAM protection, and user-adjustable reset timing - making it the only option among the three capable of full-system supervision in battery-critical applications like data loggers and industrial controllers.
Availability
LTC695ISW-3.3#PBF is available at Aetrix Electronics and suitable for industrial PLC controllers, medical data loggers, automotive telematics units, and smart energy meters requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LTC695ISW-3.3#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, acquired Linear Technology in 2017 to expand its precision power and interface portfolio.
The LTC695ISW-3.3#PBF belongs to ADI's legacy Linear Technology supervisory IC family, designed specifically for robust power monitoring and data integrity assurance in 3.3V microprocessor systems operating under harsh thermal and supply-voltage conditions.
FAQ
What is the guaranteed minimum VCC level at which LTC695ISW-3.3#PBF asserts RESET?
The LTC695ISW-3.3#PBF guarantees RESET remains logic low down to VCC = 1V with ISINK = 10μA, ensuring deterministic microprocessor shutdown even during deep brownout events where most supervisors lose functionality. This specification is tested and guaranteed over the full –40°C to +85°C operating temperature range and is a key differentiator versus standard 2.5V or 2.7V reset thresholds.
Does LTC695ISW-3.3#PBF support adjustable reset timeout, and how is it configured?
Yes, the LTC695ISW-3.3#PBF supports adjustable reset active time via an external capacitor connected between OSC IN and GND when OSC SEL is held low. The timeout follows the formula t = 1.1 × R × C, where R is internal (≈1.2MΩ). Typical values range from 140ms to >1s depending on capacitance. This feature is exclusive to the LTC695-3.3 variant and not available on the pin-compatible LTC694-3.3.
How does LTC695ISW-3.3#PBF prevent unintended battery charging during backup operation?
The LTC695ISW-3.3#PBF uses a charge-pumped NMOS power switch (M1) instead of a PNP transistor for VOUT sourcing, eliminating substrate current injection that would otherwise flow into VBATT and overcharge lithium-based backup batteries. In battery-backup mode, only junction leakage (≤1μA) reaches VBATT - a design choice validated in Linear Technology Application Note 69453fb to ensure safe, long-term battery operation.
Can LTC695ISW-3.3#PBF drive external circuitry beyond its 50mA VOUT limit?
Yes, the LTC695ISW-3.3#PBF provides a dedicated BATT ON output capable of sinking 25mA typical, designed explicitly to drive the base of an external PNP transistor (e.g., MMBT3906) that boosts VOUT current beyond the internal 50mA limit. This allows high-current RAM banks or EEPROMs to be powered reliably during backup without violating the device's safe operating area.
What is the function of CE IN and CE OUT pins on LTC695ISW-3.3#PBF, and why are they critical for data integrity?
The CE IN pin accepts a microprocessor's chip-enable or address-decoder signal, while CE OUT delivers a gated version that is forced high whenever VCC falls below 2.90V or VBATT - unconditionally disabling RAM writes during brownout. With 30ns typical propagation delay, this hardware-level write protection prevents partial writes and data corruption without software intervention, a capability absent in basic reset-only supervisors like the MAX691ACPE+.
LTC695ISW-3.3#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 2.9V
- Output:
- Open Drain or Open Collector
- Reset:
- Active High/Active Low
- Reset Timeout:
- 140ms Minimum
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
LTC695ISW-3.3#PBF FAQ
1.How can I place an order for LTC695ISW-3.3#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC695ISW-3.3#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC695ISW-3.3#PBF reliable?
The price and inventory of LTC695ISW-3.3#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC695ISW-3.3#PBF is usually 5 days.
3.What payment methods are accepted for LTC695ISW-3.3#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC695ISW-3.3#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC695ISW-3.3#PBF?
LTC695ISW-3.3#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC695ISW-3.3#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC695ISW-3.3#PBF?
For technical support, including LTC695ISW-3.3#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC695ISW-3.3#PBF requirements.
6.How does Aetrix verify that LTC695ISW-3.3#PBF is sourced from the original manufacturer or authorized distributors?
All LTC695ISW-3.3#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC695ISW-3.3#PBF meets industry standards.
7.What is the process for return or replacement of LTC695ISW-3.3#PBF?
All LTC695ISW-3.3#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC695ISW-3.3#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC695ISW-3.3#PBF part is unused and in its original packaging.
Return procedure for LTC695ISW-3.3#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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