Analog Devices Inc. LTC695ISW#TRPBF
- Part No.:
- LTC695ISW#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
LTC695ISW#TRPBF.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 16SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC695ISW#TRPBF from Analog Devices (formerly Linear Technology) is a 16-pin wide SOIC microprocessor supervisory IC with integrated battery backup, power-fail warning, watchdog timer, and RAM write protection. It features a 4.65V precision reset threshold, 200ms typical reset active time, guaranteed RESET assertion down to VCC = 1V, and operates over –40°C to +85°C. It is used in industrial controllers and battery-backed memory systems requiring reliable power monitoring.
For engineers reviewing the LTC695ISW#TRPBF datasheet, LTC695ISW#TRPBF pinout, LTC695ISW#TRPBF application, or LTC695ISW#TRPBF equivalent, key selection criteria include reset timing adjustability, dual reset outputs (RESET/RESET), CE gating for CMOS RAM write protection, and battery switchover hysteresis of 20mV - all confirmed for this specific I-grade wide-SO variant.
Technical Context
The LTC695ISW#TRPBF implements a bandgap-referenced voltage comparator (C1) for precise 4.65V ±150mV reset threshold detection with 40mV hysteresis, ensuring immunity to VCC transients. Its internal oscillator sets fixed 200ms typical reset pulse duration and supports long/short watchdog timeout periods (1.6s / 100ms typical) when OSC SEL is high.
Battery switchover uses comparator C2 to connect VOUT to VCC when VCC exceeds VBATT by ≥70mV, and to VBATT when VCC falls ≤50mV below VBATT - with 20mV hysteresis preventing oscillation near threshold. The charge-pumped NMOS switch delivers up to 50mA at <5Ω on-resistance, while the PMOS backup switch enables 1µA standby current operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reset Threshold | 4.65V typical; ensures µP reset before VCC drops below 4.75V (5% tolerance), with 40mV hysteresis to reject noise. |
| Reset Active Time | 140ms min / 200ms typ; guarantees stable µP initialization after power-up or brownout recovery. |
| VOUT Output Capability | 50mA max from VCC via NMOS switch (5Ω typical RDS(on)); supports active CMOS RAM supply during normal operation. |
| Battery Backup Current | 1µA max standby; enables multi-year backup for low-power SRAM using coin cells or supercaps. |
| Watchdog Timeout | 1.6s (long) / 100ms (short) typical; configurable via OSC SEL; forces RESET if WDI is not toggled within period. |
| Operating Temp Range | –40°C to +85°C; qualified for industrial embedded systems and automotive under-hood auxiliary modules. |
| Supply Current (Active) | 1.5mA max; minimizes primary supply loading without compromising supervision accuracy or speed. |
Pinout & Package
Package: 16-lead wide plastic SO (SW), 7.6mm × 10.3mm body, 1.27mm pitch, RoHS-compliant lead-free finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VBATT | Battery input | Accepts 2.0V–4.25V auxiliary source; triggers switchover when VCC falls below VBATT −50mV. |
| VCC | Main supply input | 5V nominal; powers internal circuitry and feeds VOUT via NMOS switch; bypass with 0.1µF capacitor. |
| VOUT | Backed-up memory supply | Delivers regulated output to RAM; sourced from VCC (NMOS) or VBATT (PMOS); requires ≥0.1µF bypass. |
| GND | Ground reference | Common return for all analog/digital functions; must be low-impedance connection. |
| BATT ON | Battery status indicator | Open-drain logic output; low when VOUT connected to VCC, high when switched to VBATT; sinks 35mA. |
| LOWLINE | Active-low line monitor | Inverts RESET logic; goes low when VCC < 4.65V; used for external power-good signaling. |
| OSC IN | Oscillator input | Accepts external clock or capacitor (with OSC SEL = low); determines reset/watchdog timing. |
| OSC SEL | Oscillator mode select | High/floating → internal oscillator (fixed timing); low → external clock/capacitor (adjustable timing). |
| RESET | Active-low reset output | Guaranteed low down to VCC = 1V; drives µP reset pin directly; short-circuit protected. |
| RESET | Active-high reset output | Complementary to RESET; used where µP requires active-high reset assertion. |
| WDO | Watchdog output | Active-low; goes low if WDI stalls; resets high on WDI transition or LOWLINE assertion. |
| CE IN | Chip enable input | Accepts µP address/decoder signal; gated through CE OUT to protect RAM writes during brownout. |
| CE OUT | Protected chip enable output | Buffered CE IN when VCC > 4.65V; forced high when VCC drops below threshold - prevents RAM corruption. |
| WDI | Watchdog input | Three-level input (high/low/floating); floating disables watchdog; transitions reset timeout counter. |
| PFO | Power-fail output | Open-drain; goes low when PFI < 1.3V; used to trigger µP shutdown before RESET asserts. |
| PFI | Power-fail input | Non-inverting comparator input; referenced to 1.3V internal bandgap; monitors external voltage divider. |
Key Features
| Feature | Design Value |
|---|---|
| Dual reset outputs | RESET (active-low) and RESET (active-high) provide interface flexibility for diverse µP families without level-shifting. |
| Adjustable reset timing | OSC SEL and OSC IN allow external capacitor or clock to modify reset active time beyond factory-fixed 200ms typical. |
| Guaranteed reset at 1V | RESET remains logic low even as VCC decays to 1V, ensuring µP stays in controlled shutdown during deep brownout. |
| RAM write protection | CE IN/CE OUT gating forces CE high during undervoltage, preventing accidental writes to battery-backed CMOS RAM. |
| Low-quiescent battery backup | 1µA max standby current enables >10-year coin-cell life for SRAM retention in always-on systems. |
| Thermal shutdown protection | Activates at ~155°C with 10°C hysteresis; prevents damage during sustained overload or poor PCB thermal design. |
Applications
| Industrial PLC Controller | Medical Data Logger |
|---|---|
Use Scenario: Maintains real-time clock and sensor calibration data during AC mains interruption or battery swap. IC Role / Device Role / Timing Role: Supervises 5V system rail, switches VOUT to backup battery, asserts RESET to halt CPU, and gates CE to freeze EEPROM writes. Use Value: Prevents data corruption during 100ms–2s power gaps; 1µA backup current extends CR2032 life to >8 years. |
Use Scenario: Preserves patient vital sign history in portable ECG monitor during battery replacement. IC Role / Device Role / Timing Role: Monitors main Li-ion supply (VBATT), detects early voltage sag via PFI, triggers PFO interrupt for graceful save, then asserts RESET. Use Value: 1.3V PFI reference enables 100mV-resolution power-fail warning; 20µs PFI response ensures timely shutdown before RAM loss. |
| Automotive Telematics Unit | Smart Energy Meter |
Use Scenario: Secures GPS position buffer and CAN message queue during vehicle ignition cycling or alternator dropout. IC Role / Device Role / Timing Role: Uses watchdog timer (WDI fed by µP heartbeat) to detect firmware lockup; forces RESET if no toggle within 1.6s. Use Value: Independent watchdog prevents silent failure; BATT ON output drives external PNP to boost VOUT current beyond 50mA for RF module backup. |
Use Scenario: Retains tariff schedule and consumption logs during grid outage in DIN-rail mounted meter. IC Role / Device Role / Timing Role: Supplies 3.3V RAM via VOUT from supercapacitor (VBATT), monitors 5V DC-DC output with PFI, asserts PFO 50ms before RESET. Use Value: Adjustable reset timing (via OSC IN) aligns with meter's 60ms firmware save window; 40mV reset hysteresis rejects load-switching noise. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX695CSA+ | 8-pin SOIC, no CE gating, no RESET, fixed 200ms reset, 1.25V PFI reference | Lacks RAM write protection and dual reset outputs; suitable only for basic reset-only designs | Choose when board space is constrained and CE/RESET functionality is unnecessary. |
| TPS3808G33DBVR | Single-channel 3.3V supervisor, no battery backup, no watchdog, 3.08V reset threshold | Designed for low-voltage µPs; cannot replace LTC695ISW#TRPBF in 5V systems with backup requirements | Select only for new 3.3V designs without battery switchover or watchdog needs. |
Compared with MAX695CSA+ and TPS3808G33DBVR, the LTC695ISW#TRPBF uniquely integrates battery switchover, dual reset outputs, CE gating, and adjustable watchdog - making it irreplaceable in systems requiring coordinated power fail warning, RAM protection, and robust brownout recovery.
Availability
LTC695ISW#TRPBF is available at Aetrix Electronics and suitable for industrial PLC controllers, medical data loggers, automotive telematics units, and smart energy meters requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LTC695ISW#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global semiconductor leader specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision instrumentation, industrial automation, and communications.
The LTC695 belongs to ADI's legacy Linear Technology microprocessor supervisory product line, engineered specifically for mission-critical power monitoring in systems demanding guaranteed reset behavior, battery-backed memory integrity, and early power-fail warning.
FAQ
What is the guaranteed minimum reset assertion voltage for LTC695ISW#TRPBF?
The LTC695ISW#TRPBF guarantees RESET remains logic low down to VCC = 1V, ensuring the microprocessor stays in a known reset state even during severe brownout conditions. This specification is explicitly tested and guaranteed across the full –40°C to +85°C operating range, independent of load or VBATT voltage.
Does LTC695ISW#TRPBF support adjustable reset timing, and how is it configured?
Yes, LTC695ISW#TRPBF supports adjustable reset timing via the OSC SEL and OSC IN pins. When OSC SEL is pulled low, an external capacitor (e.g., 47pF) between OSC IN and GND sets the reset active time per the datasheet formula. With OSC SEL high or floating, the internal oscillator fixes reset time at 200ms typical - confirmed for the LTC695ISW#TRPBF variant.
How does the CE IN/CE OUT function protect CMOS RAM in LTC695ISW#TRPBF?
In LTC695ISW#TRPBF, CE OUT is a buffered, fault-tolerant replica of CE IN during normal operation (VCC > 4.65V), but is forced high whenever VCC drops below the reset threshold or VBATT. This prevents write operations to battery-backed RAM during undervoltage, preserving data integrity - a feature absent in the 8-pin LTC694/LTC690 family.
What is the maximum continuous output current from VOUT on LTC695ISW#TRPBF?
The VOUT pin of LTC695ISW#TRPBF delivers up to 50mA continuously when powered from VCC via its internal charge-pumped NMOS switch, with a typical on-resistance of 5Ω. In battery backup mode (VCC < VBATT), VOUT supplies up to 250µA with 125Ω effective resistance - both values are specified and tested for the LTC695ISW#TRPBF device.
Can LTC695ISW#TRPBF monitor both primary supply and battery voltage simultaneously?
Yes, LTC695ISW#TRPBF independently monitors VCC (for reset generation) and VBATT (for switchover control). The PFI pin provides a third monitoring channel - referenced to a 1.3V internal bandgap - enabling simultaneous tracking of unregulated input, regulated 5V rail, or battery health via external resistor dividers, all confirmed in the LTC695 datasheet.
LTC695ISW#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 4.65V
- Output:
- Open Drain or Open Collector
- Reset:
- Active High/Active Low
- Reset Timeout:
- 140ms Minimum
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
LTC695ISW#TRPBF FAQ
1.How can I place an order for LTC695ISW#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC695ISW#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC695ISW#TRPBF reliable?
The price and inventory of LTC695ISW#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC695ISW#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC695ISW#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC695ISW#TRPBF transactions.
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4.How is shipping managed for LTC695ISW#TRPBF?
LTC695ISW#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC695ISW#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC695ISW#TRPBF?
For technical support, including LTC695ISW#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC695ISW#TRPBF requirements.
6.How does Aetrix verify that LTC695ISW#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC695ISW#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC695ISW#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC695ISW#TRPBF?
All LTC695ISW#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC695ISW#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC695ISW#TRPBF part is unused and in its original packaging.
Return procedure for LTC695ISW#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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