Analog Devices Inc. LTC7132EY#PBF
- Part No.:
- LTC7132EY#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 140-FBGA
- Datasheet:
-
LTC7132EY#PBF.pdf
- Description:
- IC REG BCK ADJ 25A/25A DL 140BGA
- Quantity:
- Payment:

- Shipping:

Inventory:2,466
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Product details
Overview
LTC7132EY#PBF from Analog Devices is a dual-output PolyPhase synchronous step-down DC/DC regulator with PMBus/I²C digital power system management. It delivers up to 25A per channel, supports 4.5V–20V input and 0.5V–5.5V output ranges, features ±0.5% output voltage accuracy over temperature, integrated input current sensing, and internal EEPROM with ECC for fault logging-used in telecom/datacom point-of-load power delivery.
For engineers reviewing the LTC7132EY#PBF datasheet, LTC7132EY#PBF pinout, LTC7132EY#PBF application, or LTC7132EY#PBF equivalent, key selection considerations include sub-milliohm DCR current sensing capability, programmable loop compensation via digital interface, independent FAULT/PGOOD per channel, 140-ball BGA package (9mm × 11.25mm), and support for up to 6-phase PolyPhase current sharing in high-density server and storage systems.
Technical Context
The LTC7132EY#PBF implements a constant-frequency current-mode control architecture optimized for ultra-low-DCR inductor sensing (down to 0.29mΩ), with independent PWM loops per channel and digitally adjustable compensation via ITH0/ITH1 and RTH0/RTH1 terminals. Its dual-channel design enables precise phase interleaving (0°–300° programmable) and synchronized switching using an external SYNC signal or internal PLL.
It integrates dedicated analog front-ends for VOUT, IOUT, VIN, IIN, and temperature telemetry with 16-bit VOUT readback resolution (244µV LSB), 10-bit current/voltage telemetry, and on-chip regulators (INTVCC, EXTVCC, VDD33, VDD25). Fault handling includes per-channel OV/UV/OC detection, thermal shutdown, and nonvolatile fault logging with CRC protection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 25A per channel; enables high-power PoL conversion without external driver stages |
| Input Voltage Range | 4.5V to 20V; compatible with 5V, 12V, and intermediate bus architectures |
| Output Voltage Range | 0.5V–3.5V (ultralow DCR mode); 0.5V–5.5V (typical DCR mode); supports DDR, ASIC, FPGA rails |
| Output Voltage Accuracy | ±0.5% over –40°C to 125°C junction; ensures stable core voltage under thermal stress |
| Switching Frequency | 250kHz–1000kHz programmable; allows optimization of efficiency vs. size trade-offs |
| PMBus Compliance | PMBus v1.3 compliant; supports telemetry read-back, sequencing, margining, and fault logging |
| Package | 140-ball BGA (9mm × 11.25mm × 2.22mm); thermally enhanced for high-power density layouts |
| EEPROM | Internal EEPROM with ECC and 10-year data retention; stores configuration and fault logs without external memory |
Pinout & Package
The LTC7132EY#PBF is housed in a 140-lead BGA package (9mm × 11.25mm × 2.22mm) with θJA = 14.5°C/W and θJC = 1.1°C/W. Five pins (B2, B4, E8, E9, F6) are NC and must be floated or grounded. Thermal pad (PGND) occupies central array region.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SVIN, PVIN0, PVIN1 | Main input power supply inputs | Accept 4.5V–20V; PVIN0/PVIN1 power respective high-side MOSFETs; SVIN powers bias circuitry |
| SW0, SW1 | Power switch node outputs | Drive external buck inductors; rated for –5V to 26V transient swing |
| VSENSE0+/VSENSE0–, VSENSE1+/VSENSE1– | Differential output voltage sense inputs | Enable remote sensing with ±0.5% accuracy; reject PCB IR drop |
| ISENSE0±, ISENSE1± | Differential current sense inputs | Support sub-milliohm DCR sensing (e.g., 0.29mΩ); selectable gain modes |
| TSNS0, TSNS1 | External temperature sensor inputs | Interface with NTC/PTC thermistors; support ∆VBE or 2VBE measurement modes |
| SDA, SCL, ALERT | PMBus/I²C serial interface | Open-drain, 400kHz max; support multi-device bus with address configuration via ASEL0/ASEL1 |
| RUN0, RUN1 | Channel enable inputs | Active-high; support independent sequencing and soft-start control per output |
| FAULT0, FAULT1, PGOOD0, PGOOD1 | Per-channel fault and power-good indicators | Open-drain outputs; configurable fault masking and latching behavior via PMBus |
| SHARE_CLK | PolyPhase current-sharing clock | Enables synchronization across up to six phases for parallel operation |
| EXTVCC, INTVCC, VDD33, VDD25 | Internal regulator outputs | Provide regulated 5.5V (INTVCC), 3.3V (VDD33), and 2.5V (VDD25) supplies for gate drivers and logic |
Key Features
| Feature | Design Value |
|---|---|
| Dual-channel PolyPhase control | Enables 50A total output with interleaved switching to reduce input/output ripple and EMI |
| Sub-milliohm DCR current sensing | Supports inductor DCR as low as 0.29mΩ without external sense resistors-reducing power loss and board area |
| Programmable loop compensation | Digital adjustment of error amplifier transconductance (gm = 0.8–4.6 mmho) and compensation resistor (0–62 kΩ) |
| Integrated input current sensing | On-chip amplifier measures total input current (IIN) with ±1.25% TUE-critical for system-level power budgeting |
| EEPROM with ECC and fault logging | Stores configuration, telemetry snapshots, and fault events with error correction-enabling post-fault diagnostics without host intervention |
| Independent sequencing and margining | Per-channel soft-start/stop, voltage ramping, and ±3% margining via PMBus-supports complex power-up/down sequences in multi-rail systems |
Applications
| Telecom/Datacom Point-of-Load | High-Density Server Power |
|---|---|
Use Scenario: Powering ASICs, FPGAs, and SerDes transceivers in 1RU/2RU servers with strict thermal and space constraints. IC Role / Device Role / Timing Role: Dual-output PolyPhase buck controller managing 1.8V and 1.0V rails with phase interleaving and real-time telemetry. Use Value: Achieves >95% peak efficiency at 20A/channel while enabling dynamic voltage scaling and fault-aware runtime monitoring via PMBus. | Use Scenario: Delivering tightly regulated 0.85V/60A CPU core voltage in cloud infrastructure platforms requiring redundancy and telemetry. IC Role / Device Role / Timing Role: Primary PoL regulator with 6-phase expansion capability via SHARE_CLK; supports time-based and voltage-based sequencing. Use Value: Reduces input capacitor count by 40% through 180° phase offset and provides per-rail fault isolation to prevent cascading failures. |
| Industrial PLC Power Management | Storage System Power Delivery |
Use Scenario: Providing isolated 3.3V and 5V rails for I/O modules and communication interfaces in harsh industrial environments. IC Role / Device Role / Timing Role: Dual-output regulator with extended temperature range (–40°C to 125°C), robust fault logging, and undervoltage lockout hysteresis. Use Value: Maintains ±0.5% output regulation across wide ambient swings and records thermal excursions for predictive maintenance. | Use Scenario: Supplying 1.2V DDR4/DDR5 memory rails and 3.3V SATA/NVMe controller power in enterprise SSDs and JBOD enclosures. IC Role / Device Role / Timing Role: High-accuracy, low-noise buck controller with ultralow DCR sensing and fast transient response (<100µs OV/UV detection). Use Value: Eliminates external current-sense resistors, reduces BOM cost by $0.32/unit, and meets JEDEC JESD22-A108 reliability standards. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output digital power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC7131EY#PBF | Single-output version; identical pinout except missing second channel's SW1, BOOST1, etc.; same 25A rating, PMBus, and package | Suitable only for single-rail systems; lacks independent FAULT1/PGOOD1 and phase synchronization capability | Select when only one high-current rail is required and board layout re-use is critical |
| MP8770GL-DS | Monolithic dual 20A buck with I²C (not PMBus-compliant); no EEPROM, no input current sensing, no sub-milliohm DCR support | Lower-cost alternative for non-telemetry applications; lacks fault logging, margining, and PolyPhase expansion | Choose for cost-sensitive embedded systems where digital management depth is secondary to basic regulation |
Compared with LTC7131EY#PBF and MP8770GL-DS, the LTC7132EY#PBF uniquely combines dual 25A channels, full PMBus v1.3 compliance, sub-milliohm DCR sensing, and nonvolatile fault logging-making it the only option for mission-critical, telemetry-driven, multi-phase PoL designs requiring field-upgradable configurations.
Availability
LTC7132EY#PBF is available at Aetrix Electronics and suitable for telecom/datacom point-of-load, high-density server power, and industrial PLC power management requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LTC7132EY#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, communications, and power management markets.
The LTC7132EY#PBF belongs to the Power by Linear™ family of digital power system management ICs, designed specifically for high-efficiency, high-density, telemetry-enabled DC/DC conversion in datacenter, networking, and industrial infrastructure equipment.
FAQ
What is the maximum supported output voltage range for the LTC7132EY#PBF?
The LTC7132EY#PBF supports two programmable output voltage ranges: 0.5V–3.5V in ultralow DCR mode (MFR_PWM_MODE[2]=1) and 0.5V–5.5V in typical DCR mode (MFR_PWM_MODE[2]=0). The upper limit depends on DCR sensing configuration and is enforced by internal DAC limits-not external components. Both ranges maintain ±0.5% accuracy over temperature.
Does the LTC7132EY#PBF require external current-sense resistors for DCR-based sensing?
No, the LTC7132EY#PBF does not require external current-sense resistors when using inductor DCR sensing. Its integrated current-sense amplifier supports sub-milliohm DCR values down to 0.29mΩ directly on ISENSE0± and ISENSE1± pins. External resistors are only needed if low-value shunts (e.g., 1mΩ) are preferred over DCR, and even then, the part provides selectable gain and offset calibration via PMBus commands.
How does the LTC7132EY#PBF handle fault conditions such as overvoltage or overtemperature?
The LTC7132EY#PBF detects overvoltage (OV), undervoltage (UV), overcurrent (OC), and overtemperature (OT) faults per channel with configurable response modes. Upon detection, it asserts FAULT0/FAULT1, logs timestamped event data to internal EEPROM with CRC, and can latch or auto-retry based on PMBus settings. Internal OT protection triggers thermal shutdown above 125°C junction, while external OT uses TSNS0/TSNS1 with user-defined thresholds.
Can the LTC7132EY#PBF operate in forced continuous conduction mode (FCCM)?
Yes, the LTC7132EY#PBF supports both discontinuous conduction mode (DCM/pulse-skipping) and forced continuous conduction mode (FCCM). Mode selection is controlled per channel via the MODE pin or PMBus command MFR_PWM_MODE[0]. FCCM eliminates low-load frequency variation and improves light-load transient response-critical for CPU core rails with dynamic current demands.
What is the purpose of the SHARE_CLK pin on the LTC7132EY#PBF?
The SHARE_CLK pin on the LTC7132EY#PBF enables PolyPhase current sharing across up to six synchronized regulators. When configured as a master, it outputs a clock signal; as a slave, it accepts that clock to align switching edges and balance current among parallel phases. This reduces input/output ripple, improves thermal distribution, and scales output current beyond 50A without redesigning magnetics or layout.
LTC7132EY#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 140-FBGA
- Packaging:
- Tray
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 20V
- Voltage - Output (Min/Fixed):
- 0.5V
- Voltage - Output (Max):
- 5.5V
- Current - Output:
- 25A, 25A
- Frequency - Switching:
- 200kHz ~ 1MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 140-BGA (11.25x9)
LTC7132EY#PBF FAQ
1.How can I place an order for LTC7132EY#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC7132EY#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC7132EY#PBF reliable?
The price and inventory of LTC7132EY#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC7132EY#PBF is usually 5 days.
3.What payment methods are accepted for LTC7132EY#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC7132EY#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC7132EY#PBF?
LTC7132EY#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC7132EY#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC7132EY#PBF?
For technical support, including LTC7132EY#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC7132EY#PBF requirements.
6.How does Aetrix verify that LTC7132EY#PBF is sourced from the original manufacturer or authorized distributors?
All LTC7132EY#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC7132EY#PBF meets industry standards.
7.What is the process for return or replacement of LTC7132EY#PBF?
All LTC7132EY#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC7132EY#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC7132EY#PBF part is unused and in its original packaging.
Return procedure for LTC7132EY#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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