Analog Devices Inc. LTC7840EFE#PBF
- Part No.:
- LTC7840EFE#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 28-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
LTC7840EFE#PBF.pdf
- Description:
- DUAL PHASE/OUTPUT NON-SYNCH BOOS
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC7840EFE#PBF from Analog Devices is a dual-phase, dual-output nonsynchronous boost controller driving external N-channel MOSFETs in high-voltage DC-DC conversion. It operates from 5.5V to 60V input, delivers programmable 50kHz–425kHz switching frequency, features ±1% 1.2V internal reference, dual RUN pins, and hiccup-mode overcurrent protection - used in automotive 48V/240V boost supplies and telecom intermediate bus converters.
For engineers reviewing the LTC7840EFE#PBF datasheet, LTC7840EFE#PBF pinout, LTC7840EFE#PBF application, or LTC7840EFE#PBF equivalent, key selection considerations include its 28-pin TSSOP package with exposed SGND pad, dual-channel current-mode control with independent ITH/SS/ILIM pins, 10V DRVCC gate driver LDO, and configurable operation for boost, SEPIC, or flyback topologies.
Technical Context
The LTC7840EFE#PBF implements constant-frequency peak current-mode control with smooth quadratic slope compensation and dynamic slope recovery per channel. Its two independent control loops operate 180° out-of-phase, each with dedicated VFB, ITH, SS, RUN, PGOOD, and current-sense inputs (SENSE+/−).
It integrates cascaded LDOs: a 10V DRVCC regulator (powered from VIN) for gate drivers and a 3.8V INTVCC regulator (powered from DRVCC) for analog/digital circuitry. The device supports external synchronization via SYNC pin (50kHz–450kHz), phase-lockable frequency programming via FREQ pin, and adjustable max duty cycle (75–96%) and minimum on-time (120–200ns) via DMAX and BLANK pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 5.5V to 60V - accommodates automotive load dump surges and industrial wide-input rails without external pre-regulation. |
| Switching Frequency | 50kHz to 425kHz - programmable via FREQ pin voltage or synchronized externally; enables optimization of size vs. efficiency in high-voltage boost designs. |
| Internal Reference | ±1% at 1.2V - ensures precise output voltage regulation across temperature and line/load variations in dual-output configurations. |
| DRVCC LDO Output | 10V ±0.4V - powers high-side N-MOSFET gates directly; supports RDS(ON) optimized for 6V–10V VGS, eliminating need for external gate driver supply. |
| Current Sense Threshold | 70mV to 80mV (typ. 75mV) - sets overcurrent trip point; adjustable via ILIM1/ILIM2 pins with 10µA sink current for fine-tuned protection thresholds. |
| Max Duty Cycle | 75% / 84% / 96% - selected by DMAX pin voltage (INTVCC / float / SGND); prevents shoot-through and enables safe operation near VIN/VOUT limits. |
| Min On-Time | 120ns / 160ns / 200ns - set by BLANK pin (SGND / float / INTVCC); ensures stable operation at high VOUT/VIN ratios and light loads. |
| Operating Temp Range | –40°C to +125°C - specified for industrial and automotive under-hood applications; junction-limited reliability validated per ADI characterization. |
Pinout & Package
The LTC7840EFE#PBF is housed in a 28-lead thermally enhanced TSSOP package (FE28) with exposed SGND pad (Pin 29), requiring soldering to PCB for thermal and electrical integrity. θJA = 30°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| BLANK (Pin 1) | Minimum on-time configuration | Setting to SGND/float/INTVCC selects 120ns/160ns/200ns min on-time - critical for stability at high step-up ratios (e.g., 12V→240V). |
| GATE1/GATE2 (Pins 21,19) | N-MOSFET gate drive outputs | 10V CMOS-compatible outputs referenced to PGND - drive high-voltage power switches without level-shifting or external drivers. |
| SENSE1+/SENSE1−, SENSE2+/SENSE2− (Pins 28,27,14,15) | Differential current sense inputs | Measure MOSFET source current via external sense resistor - enable per-channel overcurrent protection and current-mode loop stability. |
| ILIM1/ILIM2 (Pins 26,16) | Current limit threshold programming | 10µA sink current allows resistor-to-SGND setting of max sense voltage (≤75mV) - configures OCP trip point independently per channel. |
| RUN1/RUN2 (Pins 9,10) | Channel enable control | 1.22V turn-on threshold with 80mV hysteresis - supports independent sequencing, fault shutdown, or power-good interlocking between channels. |
| PGOOD1/PGOOD2 (Pins 18,17) | Open-drain power-good indicators | Assert low after 135µs mask time when VFB is within ±10% of target - provides reliable system-level rail monitoring for microcontrollers or supervisors. |
| DRVCC (Pin 22) | Gate driver LDO output | 10V regulated supply for GATE1/GATE2 - must be bypassed with ≥4.7µF ceramic capacitor to PGND; powers up only after VIN UVLO release. |
| INTVCC (Pin 25) | Control circuit LDO output | 3.8V supply for internal analog/digital blocks - bypassed with 1nF capacitor to SGND; powered from DRVCC, not VIN, preventing latch-up during startup. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-phase 180° interleaving | Reduces input/output ripple current by ~70% vs. single-phase, enabling smaller EMI filters and bulk capacitors in high-power boost converters. |
| Hiccup-mode overcurrent protection | Auto-restarts after fault clearance - prevents thermal runaway during sustained overload or short-circuit conditions without latching off. |
| Configurable topology support | Validated for boost, SEPIC, and flyback - allows reuse of same controller IC across multiple isolated/non-isolated high-VOUT architectures. |
| Independent soft-start ramping | SS1/SS2 pins accept 10µA charge current - enables staggered or matched output voltage ramp-up to avoid inrush current conflicts in dual-rail systems. |
| Programmable blanking time & max duty cycle | BLANK and DMAX pins allow tuning of timing margins - essential for robust operation with fast-switching SiC/GaN FETs or high-VOUT/VIN ratios. |
| Integrated cascaded LDO architecture | DRVCC → INTVCC power chain eliminates external bias supplies - simplifies BOM while enforcing safe power-up sequencing and preventing body-diode conduction faults. |
Applications
| Automotive 48V Mild Hybrid Boost | Telecom Intermediate Bus Converter |
|---|---|
Use Scenario: Step-up 12V battery to 48V rail for electric turbochargers and active suspension in 48V mild hybrid vehicles. IC Role / Device Role / Timing Role: Dual-phase nonsynchronous boost controller managing two parallel 12V→48V stages with interleaved switching and independent current limiting. Use Value: Achieves >92% efficiency at 1.2A output while meeting automotive AEC-Q100 temp range (–40°C to +125°C) and surviving 60V load dump transients. | Use Scenario: Generating 240V intermediate bus from 24V telecom rectifier for downstream high-voltage PoE++ or RF power amplifiers. IC Role / Device Role / Timing Role: Dual-output controller operating in dual-phase single-output mode to deliver 240V/0.7A with reduced input ripple and thermal stress. Use Value: Enables compact 2-layer PCB design using 28-pin TSSOP package and eliminates need for external gate drivers or bias supplies. |
| Industrial High-Voltage Sensor Supply | Test Equipment Programmable HV Source |
Use Scenario: Providing stable 36V and 48V isolated sensor bias rails from 9–36V industrial input in factory automation systems. IC Role / Device Role / Timing Role: Dual-output boost controller regulating two independent outputs with separate VFB/PGOOD/SS pins for flexible rail sequencing. Use Value: Delivers ±1% output accuracy across line/load/temperature using internal 1.2V reference - eliminates need for external DACs or trimming. | Use Scenario: Building benchtop HV power supply with digitally adjustable 0–200V output and current limiting for semiconductor characterization. IC Role / Device Role / Timing Role: Configured in SEPIC topology to support output voltages both above and below input, with hiccup-mode protection during device under-test faults. Use Value: Supports remote frequency sync (via SYNC pin) and analog voltage programming (via FREQ/DMAX/ILIM) for closed-loop digital control interfaces. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-phase boost controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC7841EFE#PBF | Synchronous boost controller with integrated gate drivers; supports lower VOUT/VIN ratios; no external diode required. | Better efficiency below 100V output; unsuitable for >200V due to synchronous rectifier voltage limits. | Select LTC7841EFE#PBF when efficiency >94% at <100V output is critical and external diodes are undesirable. |
| LM5122MH/NOPB | Single-channel, wide-VIN boost controller; 3.5V–65V input; no dual-phase or hiccup-mode; different pinout and compensation scheme. | Requires two ICs for dual-output; lacks channel interleaving, independent RUN/PGOOD, and programmable blanking. | Select LM5122MH/NOPB only for cost-sensitive single-rail designs where dual-phase benefits are unnecessary. |
Compared with LTC7841EFE#PBF, the LTC7840EFE#PBF trades synchronous rectification for higher-voltage capability and external diode flexibility; compared with LM5122MH/NOPB, it delivers true dual-channel integration, interleaving, and fault management - making it optimal for space-constrained, high-VOUT, and safety-critical dual-rail systems.
Availability
LTC7840EFE#PBF is available at Aetrix Electronics and suitable for automotive 48V systems, telecom intermediate bus converters, and industrial high-voltage sensor supplies requiring stable component supply, long-term lifecycle support, and AEC-Q100-aligned qualification.
Supply support for LTC7840EFE#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTC7840EFE#PBF belongs to ADI's Power by Linear™ controller family, designed specifically for high-voltage, high-efficiency DC-DC conversion in demanding environments where reliability, precision, and thermal robustness are mandatory.
FAQ
What is the maximum output voltage achievable with the LTC7840EFE#PBF?
The LTC7840EFE#PBF itself does not impose a hard upper limit on output voltage - it is a controller, not a power stage. Output voltage is determined by external components: inductor value, output capacitor voltage rating, MOSFET breakdown voltage, and external diode PIV rating. Application circuits demonstrate stable operation up to 240V (e.g., 12V→240V boost), constrained only by component selection and layout. The LTC7840EFE#PBF's 60V VIN rating and 10V gate drive support high-side N-MOSFETs rated ≥250V VDSS.
Does the LTC7840EFE#PBF support synchronization to an external clock?
Yes, the LTC7840EFE#PBF supports external clock synchronization via the SYNC pin (Pin 3). It accepts TTL/CMOS-compatible signals from 50kHz to 450kHz, locking both channels' switching frequency and phase to the external source. The internal PLL includes integrated compensation, requiring no external components. This feature enables noise-sensitive systems to avoid beat frequencies and facilitates multi-phase stacking in high-power supplies using CLKOUT daisy-chaining.
How is overcurrent protection implemented in the LTC7840EFE#PBF?
The LTC7840EFE#PBF implements per-channel overcurrent protection using high-side current sensing via SENSE1+/− and SENSE2+/− pins, with trip threshold set by ILIM1/ILIM2 pins (default 75mV). Upon current limit violation, it enters hiccup mode: switching halts, SS1/SS2 pins discharge, and after a timeout set by SS capacitor value, restart attempts occur. This prevents thermal runaway during sustained faults while allowing automatic recovery - distinct from latch-off protection. The LTC7840EFE#PBF also includes output overvoltage lockout (VOVL) triggered at ±12.5% VFB.
Can the LTC7840EFE#PBF be used in SEPIC or flyback topologies?
Yes, the LTC7840EFE#PBF is explicitly qualified for SEPIC and flyback configurations per its datasheet. Its nonsynchronous architecture, independent current-sense inputs, and flexible gate drive timing allow reconfiguration beyond boost: for SEPIC, connect coupled inductors and adjust feedback divider; for flyback, route primary-side sensing and use transformer reset winding or RCD clamp. Design Note DN542 and LTspice models confirm stable operation in both topologies - leveraging the same LTC7840EFE#PBF pin functions and compensation methodology.
What is the purpose of the exposed pad (Pin 29) on the LTC7840EFE#PBF TSSOP package?
The exposed pad (Pin 29) on the LTC7840EFE#PBF TSSOP package is internally connected to SGND and serves dual thermal and electrical roles. Electrically, it provides low-inductance return path for sensitive analog ground currents (VFB, ITH, SS). Thermally, it conducts heat from the die to the PCB copper plane - reducing θJA from 30°C/W to ≤15°C/W with proper thermal vias and copper area. Per ADI layout guidelines, this pad must be soldered to a dedicated SGND plane with ≥4 thermal vias (0.3mm diameter) to ensure reliability and meet –40°C to +125°C junction temperature specifications.
LTC7840EFE#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Output Type:
- PWM
- Function:
- Step-Up
- Output Configuration:
- Positive
- Topology:
- Boost
- Number of Outputs:
- 2
- Output Phases:
- 2
- Voltage - Supply (Vcc/Vdd):
- 5.5V ~ 60V
- Frequency - Switching:
- 50kHz ~ 425kHz
- Duty Cycle (Max):
- 96%
- Synchronous Rectifier:
- No
- Clock Sync:
- Yes
- Serial Interfaces:
- -
- Control Features:
- Current Limit, Enable, Frequency Control, Power Good
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSSOP-EP
LTC7840EFE#PBF FAQ
1.How can I place an order for LTC7840EFE#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC7840EFE#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC7840EFE#PBF reliable?
The price and inventory of LTC7840EFE#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC7840EFE#PBF is usually 5 days.
3.What payment methods are accepted for LTC7840EFE#PBF?
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4.How is shipping managed for LTC7840EFE#PBF?
LTC7840EFE#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC7840EFE#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC7840EFE#PBF?
For technical support, including LTC7840EFE#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC7840EFE#PBF requirements.
6.How does Aetrix verify that LTC7840EFE#PBF is sourced from the original manufacturer or authorized distributors?
All LTC7840EFE#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC7840EFE#PBF meets industry standards.
7.What is the process for return or replacement of LTC7840EFE#PBF?
All LTC7840EFE#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC7840EFE#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC7840EFE#PBF part is unused and in its original packaging.
Return procedure for LTC7840EFE#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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