Analog Devices Inc. LTC7851IUHH-1#PBF
- Part No.:
- LTC7851IUHH-1#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 58-WFQFN Exposed Pad
- Datasheet:
-
LTC7851IUHH-1#PBF.pdf
- Description:
- IC REG CTRLR BUCK 58QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC7851IUHH-1#PBF from Analog Devices is a quad-output, multiphase synchronous step-down voltage mode DC/DC controller optimized for DrMOS power stages. It delivers accurate current sharing across up to four phases, supports 250kHz–2.25MHz switching frequency, operates with VIN from 3V to 27V, and regulates outputs from 0.6V to VCC–0.5V - enabling high-current FPGA/DSP core supplies such as 1V/90A and 1.5V/30A.
For engineers reviewing the LTC7851IUHH-1#PBF datasheet, LTC7851IUHH-1#PBF pinout, LTC7851IUHH-1#PBF application, or LTC7851IUHH-1#PBF equivalent, key selection considerations include its lower-current-sense-amplifier-gain architecture (4V/V), compatibility with integrated current-sense DrMOS devices, 58-lead 5mm × 9mm QFN package, ±0.75% reference accuracy, and phase-lockable oscillator with 45° CLKOUT-to-PWM1 alignment.
Technical Context
The LTC7851IUHH-1#PBF employs a constant-frequency voltage-mode control architecture with independent error amplifiers per channel and a dedicated internal current-sharing loop. Its differential voltage sense amplifiers (VSNSP/VSNSN) enable remote sensing with offset cancellation, while the IAVG bus integrates master-slave average current signals for precise per-phase current balancing.
It features lossless DCR or precision resistor-based current sensing, with a 150mV maximum differential sense voltage and ±3mV input-referred offset over –40°C to 125°C. The device supports multiphase expansion via CLKIN/CLKOUT daisy-chaining and offers programmable soft-start, output tracking, and 128-cycle overcurrent fault detection with automatic recovery.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Range | 3V to 27V - supports wide-input industrial and telecom power rails without external VIN divider. |
| VOUT Range | 0.6V to VCC–0.5V - enables sub-1V core regulation for modern FPGAs and ASICs. |
| Switching Frequency | 250kHz to 2.25MHz - adjustable via FREQ pin resistor or external CLKIN; enables compact magnetics and high transient response. |
| Current Sense Gain | 4V/V - specifically optimized for DrMOS devices with internal current sense, reducing gain-related noise sensitivity vs. LTC7851 (20V/V). |
| Reference Accuracy | ±0.75% at 0.6V - ensures tight output regulation across temperature and line variations in high-precision core supplies. |
| Operating Temp | –40°C to +125°C junction - qualified for industrial and embedded computing environments with full performance guarantee. |
| Package | 58-lead 5mm × 9mm QFN with exposed thermal pad - provides low θJA = 49°C/W for high-power density designs. |
Pinout & Package
Package: 58-lead plastic QFN (5mm × 9mm, 0.4mm pitch), exposed pad (Pin 59) tied to SGND and required for thermal performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| COMP1–COMP4 (Pins 1,9,13,20) | Error amplifier output | Drives PWM comparator; low-impedance op-amp output - must not be directly paralleled unless FB disabled on slave channels. |
| VSNSP1–VSNSP4 (Pins 2,8,14,19) | Differential sense non-inverting input | Connects to feedback divider midpoint at load - enables accurate remote sensing by rejecting ground path offsets. |
| VSNSN1–VSNSN4 (Pins 3,7,15,18) | Differential sense inverting input | Connects to load ground - completes differential measurement; float for slave channels. |
| PWM1–PWM4 (Pins 52,50,26,24) | Top gate drive output | Three-state compatible signal for DrMOS/gate driver interface; minimum on/off times prevent shoot-through. |
| IAVG1–IAVG4 (Pins 47,42,35,30) | Average current monitor | Master channel sources 20µA; slave pins connect to master IAVG bus - implements analog current-sharing loop. |
| ILIM1–ILIM4 (Pins 48,41,36,29) | Overcurrent threshold set | Resistor-to-SGND sets OC trip point; only master ILIM sources 20µA - ensures consistent protection across phases. |
Key Features
| Feature | Design Value |
|---|---|
| DrMOS-optimized current sense | 150mV full-scale range and 4V/V gain - matches typical DrMOS current-sense output levels, minimizing noise amplification. |
| Quad-channel differential remote sensing | Four independent VSNSP/VSNSN pairs - eliminates PCB trace IR drop errors for multi-rail systems with distributed loads. |
| Phase-locked multiphase expansion | CLKIN/CLKOUT synchronization with 45° fixed phase offset - enables seamless daisy-chaining of multiple LTC7851IUHH-1#PBF for >4-phase operation. |
| Accurate current sharing | IAVG bus with 100pF typical capacitor - achieves <±3% inter-phase current mismatch under dynamic load steps. |
| Robust overcurrent protection | 128-cycle consecutive fault detection with 7-cycle hysteresis - prevents false trips during startup or transients while ensuring fast shutdown on hard shorts. |
Applications
| FPGA Core Supply | DSP Power Delivery |
|---|---|
Use Scenario: Powering Xilinx Versal or Intel Stratix 10 FPGA cores requiring tightly regulated 0.8V–1.2V at up to 100A with fast load-step response. IC Role / Device Role / Timing Role: Quad-phase voltage mode controller managing four parallel DrMOS power stages with synchronized PWM and shared current sensing. Use Value: Enables single-chip solution for high-current core rail with <50mV droop under 50A/µs load step, eliminating need for discrete current-sharing ICs. |
Use Scenario: Delivering 1.1V/40A to TI C66x or ADI SHARC+ DSP processors in radar or baseband processing units. IC Role / Device Role / Timing Role: Multiphase controller with tracking-enabled soft-start coordinating multiple output ramps to meet DSP boot sequencing requirements. Use Value: Ensures monotonic voltage ramp and <±1% cross-regulation between auxiliary and core rails during cold start. |
| AI Accelerator Module | High-Density Server VR |
Use Scenario: Providing 0.75V/80A to NVIDIA A100 GPU memory interfaces in edge inference servers with strict thermal constraints. IC Role / Device Role / Timing Role: Four-phase controller using DCR current sensing and thermal-aware phase shedding via RUN pin control. Use Value: Achieves >92% peak efficiency at 60A and maintains <5°C phase-to-phase temperature delta under sustained load. |
Use Scenario: Generating 1.8V/30A and 1.0V/90A simultaneously for CPU I/O and core domains in 1U cloud servers. IC Role / Device Role / Timing Role: Dual-output controller operating two independent 2-phase banks with shared VIN, separate FB loops, and coordinated PGOOD assertion. Use Value: Reduces BOM count by 33% vs. dual single-output controllers while maintaining independent regulation and fault isolation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multiphase step-down controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC7851IUHH#PBF | Higher current sense gain (20V/V) and 50mV max sense voltage - suited for discrete RSENSE or low-DCR inductors. | Requires external sense resistor or ultra-low-DCR inductor; less optimal for DrMOS with integrated sense. | Select when using discrete MOSFETs or power blocks without internal current sense. |
| MP2960AGQSE-LF-Z | Single-chip 4-phase controller with integrated drivers; 0.6V–1.8V output range; no external gate drive needed. | Eliminates external DrMOS but lacks independent output control and remote sensing flexibility. | Select for space-constrained designs where integration outweighs configurability needs. |
Compared with LTC7851IUHH#PBF, the LTC7851IUHH-1#PBF trades higher sense gain for improved DrMOS compatibility and reduced noise susceptibility, while MP2960AGQSE-LF-Z replaces external driver dependency with monolithic integration - making LTC7851IUHH-1#PBF optimal for high-performance, thermally managed DrMOS-based systems requiring design flexibility.
Availability
LTC7851IUHH-1#PBF is available at Aetrix Electronics and suitable for high-current FPGA core supplies, AI accelerator modules, and server voltage regulator applications requiring stable component supply, extended temperature support, and long-term production continuity.
Supply support for LTC7851IUHH-1#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and computing markets.
The LTC7851/LTC7851-1 product line was designed for high-efficiency, high-current multiphase DC/DC conversion in datacenter, AI, and high-end computing systems - emphasizing precision current sharing, DrMOS interoperability, and thermal robustness.
FAQ
What distinguishes LTC7851IUHH-1#PBF from the standard LTC7851IUHH#PBF?
The LTC7851IUHH-1#PBF features a lower current sense amplifier gain of 4V/V (vs. 20V/V in LTC7851IUHH#PBF) and a higher 150mV maximum differential sense voltage - specifically engineered to interface directly with DrMOS devices that provide integrated current-sense signals. This reduces gain-induced noise sensitivity and simplifies layout for DrMOS-based designs, while maintaining identical pinout, package, and functional architecture.
Can LTC7851IUHH-1#PBF operate with discrete MOSFETs instead of DrMOS?
Yes, LTC7851IUHH-1#PBF can drive discrete N-channel MOSFETs via external gate drivers, but its 4V/V current sense gain is suboptimal for low-voltage sense resistors or DCR networks. For discrete-FET designs, LTC7851IUHH#PBF (20V/V gain) is preferred. When using LTC7851IUHH-1#PBF with discretes, ensure the sense signal amplitude remains within 0–150mV full-scale to avoid saturation or reduced dynamic range.
How does the IAVG current-sharing bus work across multiple LTC7851IUHH-1#PBF ICs?
When daisy-chaining multiple LTC7851IUHH-1#PBF controllers, all IAVG pins (master and slaves) are connected together. Only the master channel's IAVG pin sources 20µA; slave IAVG pins sink current proportional to their instantaneous phase current error relative to the master. A single 100pF capacitor from the IAVG bus to SGND stores the averaged master current voltage, which each slave uses to adjust duty cycle - achieving <±3% current matching across up to 16 phases.
What is the purpose of the VSNSP/VSNSN pins on LTC7851IUHH-1#PBF?
The VSNSP/VSNSN pins implement a dedicated differential amplifier per channel to measure output voltage at the load point, rejecting PCB trace resistance and ground bounce. VSNSP connects to the feedback divider midpoint at the load, VSNSN to load ground - their difference drives VSNSOUT, which feeds the FB pin. This architecture ensures ±0.75% regulation accuracy regardless of board layout, unlike single-point sensing which suffers from IR drop errors.
Does LTC7851IUHH-1#PBF support output voltage tracking during startup?
Yes, LTC7851IUHH-1#PBF supports coincident tracking via the TRACK/SS pins. By connecting a resistor divider from a primary output to the TRACK/SS pin of a secondary channel - with divider ratios matching the respective feedback networks - both outputs ramp simultaneously with matched slew rates. This ensures safe sequencing for multi-rail processors like FPGAs, preventing latch-up or back-powering during power-up.
LTC7851IUHH-1#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 58-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Output Type:
- PWM Signal
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Number of Outputs:
- 4
- Output Phases:
- 1
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Frequency - Switching:
- 250kHz ~ 3MHz
- Duty Cycle (Max):
- 91.5%
- Synchronous Rectifier:
- No
- Clock Sync:
- No
- Serial Interfaces:
- -
- Control Features:
- Current Limit, Enable, Frequency Control, Power Good, Soft Start, Tracking
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 58-QFN (5x9)
LTC7851IUHH-1#PBF FAQ
1.How can I place an order for LTC7851IUHH-1#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC7851IUHH-1#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC7851IUHH-1#PBF reliable?
The price and inventory of LTC7851IUHH-1#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC7851IUHH-1#PBF is usually 5 days.
3.What payment methods are accepted for LTC7851IUHH-1#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC7851IUHH-1#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC7851IUHH-1#PBF?
LTC7851IUHH-1#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC7851IUHH-1#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC7851IUHH-1#PBF?
For technical support, including LTC7851IUHH-1#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC7851IUHH-1#PBF requirements.
6.How does Aetrix verify that LTC7851IUHH-1#PBF is sourced from the original manufacturer or authorized distributors?
All LTC7851IUHH-1#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC7851IUHH-1#PBF meets industry standards.
7.What is the process for return or replacement of LTC7851IUHH-1#PBF?
All LTC7851IUHH-1#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC7851IUHH-1#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC7851IUHH-1#PBF part is unused and in its original packaging.
Return procedure for LTC7851IUHH-1#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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