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Analog Devices Inc. LTC7852EUFD-1#PBF
- Part No.:
- LTC7852EUFD-1#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 36-WFQFN Exposed Pad
- Datasheet:
-
LTC7852EUFD-1#PBF.pdf
- Description:
- 6-PHASE BUCK CONTROLLER DRIVES D
- Quantity:
- Payment:
- Shipping:
Inventory:2,836
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Product details
Overview
LTC7852EUFD-1#PBF from Analog Devices is a dual-output, 6-phase current-mode synchronous step-down controller optimized for DrMOS-based power delivery, supporting 0.5V–2.0V output voltage range, ±0.5% total output voltage accuracy, 40ns minimum on-time, and programmable switching frequency from 250kHz to 1.2MHz in a 36-lead (4mm × 5mm) QFN package.
For engineers reviewing the LTC7852EUFD-1#PBF datasheet, LTC7852EUFD-1#PBF pinout, LTC7852EUFD-1#PBF application, or LTC7852EUFD-1#PBF equivalent, this page delivers verified technical context, validated pin functions, confirmed DrMOS-specific current sensing architecture, and real-world multiphase design constraints - all grounded in the official Rev. B datasheet and Analog Devices' application documentation.
Technical Context
The LTC7852EUFD-1#PBF implements a dedicated DrMOS interface with internal 1.5V SNSN bias rail, eliminating external DCR sense networks and enabling precise current monitoring via integrated differential amplifiers and dual remote-sense inputs per output. Its phase configuration logic (PHCFG) supports 3+3, 4+2, and 5+1 interleaving modes with fixed phase offsets defined per mode.
It uses a proprietary current-mode control loop with ITH-based peak-current regulation, hiccup-mode overcurrent protection, and synchronized soft-start via SS pins with 5µA internal pull-up. The PLLIN/CLKOUT interface enables multichip synchronization up to 12 phases without external loop filters, while FREQ pin sourcing 20µA allows resistor-programmed oscillator tuning across its full 250kHz–1.2MHz range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VOUT Range | 0.5V to 2.0V - set by external feedback divider; regulated via dual differential remote-sense amplifiers referenced to local ground. |
| tON(MIN) | 40ns - enables high-frequency operation at low duty cycles (e.g., 12V→0.9V @ 1MHz), critical for high-step-down-ratio server VRMs. |
| fSW Range | 250kHz to 1.2MHz - programmed via resistor to GND on FREQ pin; 20µA source current ensures stable, temperature-compensated frequency setting. |
| Voltage Accuracy | ±0.5% total - includes line, load, and temperature variation; achieved using precision 500mV internal reference and low-offset diff-amps. |
| VCC Range | 4.5V to 5.5V - powers internal logic and gate drivers; UVLO threshold is 4.0V with 200mV hysteresis for robust startup. |
| Package | 36-lead (4mm × 5mm) plastic QFN - exposes thermal pad for PCB soldering; θJA = 43°C/W supports high-power density layouts. |
| Current Sense | DrMOS-only interface - SNSN pins internally biased to 1.5V; eliminates need for external DCR sense resistors or RC filters. |
Pinout & Package
36-lead (4mm × 5mm) plastic QFN package with exposed thermal pad (Pin 37), rated for –40°C to +125°C junction temperature. Thermal pad must be soldered to PCB ground plane for rated thermal performance (θJA = 43°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC (Pin 13) | Bias supply input | Accepts 4.5V–5.5V external supply; powers internal regulators and logic; requires local 0.1–1µF ceramic bypass. |
| PHCFG (Pin 14) | Phase configuration select | Ground = 4+2 mode; float = 3+3 mode; VCC = 5+1 mode - determines PWM phase interleaving pattern between outputs. |
| FREQ (Pin 15) | Oscillator frequency set | Sources 20µA; resistor to GND sets fSW from 250kHz to 1.2MHz; no external capacitor required. |
| ILIM1/ILIM2 (Pins 16, 12) | Current limit threshold select | Analog inputs that scale internal current comparator threshold from 45mV to 157.5mV in five discrete steps for DrMOS compatibility. |
| RUN1/RUN2 (Pins 17, 11) | Enable control inputs | 1.22V threshold with 140mV hysteresis; internal 1.3µA pull-up on release; supports sequencing and fault shutdown. |
| VOSNS1+/VOSNS2+ (Pins 19, 10) | Differential remote sense non-inverting | Connect to feedback divider center tap; forms unity-gain diff-amp pair with VOSNS– to reject IR drop in PCB traces. |
| VOSNS1–/VOSNS2– (Pins 20, 9) | Differential remote sense inverting | Connect to load ground point; matched routing with VOSNS+ essential for <1mV offset and accurate regulation. |
| ITH1/ITH2 (Pins 21, 8) | Error amplifier output / compensation node | Carries error signal driving current comparator threshold; also serves as compensation point for Type II/III loop filters. |
| SS1/SS2 (Pins 22, 7) | Soft-start ramp input | 5µA internal current charges external capacitor; 0–0.5V ramp controls output voltage slew rate; min 22nF required. |
| PGOOD1/PGOOD2 (Pins 23, 6) | Power-good open-drain outputs | Pull low when VOUT deviates >±7.5% from target; 200Ω on-resistance; 2µA leakage at 5V; supports system sequencing. |
| SNSP1–SNSP6 (Pins 24, 26, 27, 3, 4, 5) | Positive current sense inputs | Accept differential current monitor signals from DrMOS devices; each pair shares common SNSN bias. |
| SNSN (Pins 2, 25) | Internal 1.5V current sense bias | DrMOS-specific rail - provides common-mode voltage for all six SNSP inputs; not available on LTC7852 (non-1 variant). |
| PWM1–PWM6 (Pins 30–35) | Top-gate drive outputs | Three-state compatible; logic-high level equals VDD (3.3V); drives external gate drivers or DrMOS enable inputs directly. |
| VDD (Pin 28) | Internally regulated 3.3V supply | Bypass with 2.2µF low-ESR capacitor; supplies PWM logic; may be externally biased to adjust HIGH-level voltage if needed. |
| CLKOUT (Pin 29) | Master clock output | Provides synchronized timing signal for cascading multiple controllers; aligns rising edge of PWM1 with PLLIN input in locked state. |
| PLLIN (Pin 1) | External clock synchronization input | Accepts 250kHz–1.2MHz external clock; integrates PLL loop filter; locks internal oscillator with <1° phase jitter. |
| GND (Pin 36) | Analog/digital ground reference | Primary return for small-signal circuitry; all compensation and sense components must tie here; exposed pad (Pin 37) is GND. |
Key Features
| Feature | Design Value |
|---|---|
| DrMOS-optimized current sensing | Integrated 1.5V SNSN bias rail eliminates external DCR networks, reduces layout sensitivity, and improves SNR for high-efficiency server VRMs. |
| Dual independent remote sensing | Two fully isolated differential amplifiers (VOSNS1±, VOSNS2±) enable precise 0.5V–2.0V regulation per output under dynamic load, rejecting PCB trace IR drop. |
| Flexible multiphase interleaving | Hardware-selectable 3+3, 4+2, or 5+1 phase splits with fixed inter-phase angles (e.g., 60°/120° in 3+3 mode) minimize input/output ripple and improve thermal distribution. |
| Programmable ultra-low tON(MIN) | 40ns minimum on-time supports 12V→0.9V conversion at 1MHz, enabling compact magnetics and high-density board layouts in datacenter applications. |
| Integrated PLL synchronization | On-die PLL with integrated loop filter enables deterministic multichip phase alignment - up to 12 phases with zero external components beyond CLKOUT/PLLIN connection. |
| Hiccup-mode overcurrent protection | Auto-retry shutdown during sustained overloads limits thermal stress on MOSFETs and DrMOS, preserving reliability in telecom and AI accelerator power systems. |
Applications
| AI Accelerator VRM | Server CPU Core Power |
|---|---|
|
Use Scenario: High-current, low-voltage core supply for NVIDIA H100 or AMD MI300X GPUs requiring rapid transient response and tight voltage tolerance under 1000A peak loads. IC Role / Device Role / Timing Role: Dual-output 6-phase controller managing two independent 3+3 phase rails - one for GPU core, one for memory interface - with synchronized CLKOUT/PLLIN for system-wide timing coherence. Use Value: Enables sub-1mΩ DCR-less DrMOS sensing, achieving ±0.5% regulation accuracy and 40ns tON(MIN) for 1MHz operation, reducing output capacitance by 30% vs. legacy controllers. |
Use Scenario: Primary core voltage regulator for Intel Xeon Scalable or AMD EPYC processors in 1U/2U rack servers, where thermal density and EMI compliance are critical. IC Role / Device Role / Timing Role: Configured in 4+2 mode to deliver asymmetric current (120A/60A) across two outputs while interleaving phases to suppress 24th harmonic input ripple. Use Value: Dual remote sensing rejects PCB voltage drop across long motherboard traces, maintaining 0.85V ±4.25mV at socket under 200A load steps, meeting Intel VRD14 specs. |
| High-Density Telecom PSU | Edge AI Inference Module |
|
Use Scenario: Compact 48V-to-12V intermediate bus converter feeding distributed POLs in 5G baseband units, constrained by strict size and thermal limits. IC Role / Device Role / Timing Role: Operates as single-output 6-phase controller (PHCFG floated) driving parallel DrMOS stages; CLKOUT synchronized to system master clock for EMI spreading. Use Value: 36-pin QFN footprint (4mm × 5mm) saves 35% board area vs. 48-pin GQFN variants; 43°C/W θJA enables 85°C ambient operation without forced air. |
Use Scenario: Power management for embedded vision accelerators (e.g., Qualcomm Cloud AI 100) in fanless edge servers, requiring silent operation and fast load-step recovery. IC Role / Device Role / Timing Role: Dual-output controller delivering 0.75V@60A (core) and 1.8V@20A (I/O) with independent soft-start (SS1/SS2) and PGOOD sequencing. Use Value: Independent RUN1/RUN2 and PGOOD1/PGOOD2 support staggered power-up of core and I/O domains, preventing inrush current overload on shared 12V input rail. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output multiphase controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL91302BIRZ-T7A | Single-chip dual-output buck controller with integrated MOSFET drivers; supports 0.3V–5.5V VOUT; no DrMOS-specific SNSN rail; max fSW = 3MHz but tON(MIN) = 60ns. | Targeted at portable/battery-powered systems; lacks PLLIN/CLKOUT sync capability and remote sensing; lower current capability (≤60A per rail). | Select when board space is paramount and DrMOS integration is not required; avoid for high-current server VRMs needing phase synchronization. |
| MP2965EK-LF-P | 6-phase digital controller with PMBus interface; supports DCR and DrMOS sensing; tON(MIN) = 50ns; fSW up to 1.5MHz; requires external EEPROM for configuration. | Designed for programmable, telemetry-enabled systems; adds digital loop tuning and fault logging; higher BOM cost and firmware dependency. | Choose when digital control, real-time telemetry, or field-upgradable parameters are mandatory; not suitable for analog-only designs or cost-sensitive volume production. |
Compared with ISL91302BIRZ-T7A and MP2965EK-LF-P, the LTC7852EUFD-1#PBF delivers superior DrMOS-native signal integrity, deterministic hardware-based phase alignment, and tighter analog voltage accuracy - making it the preferred choice for high-reliability, high-current infrastructure power where analog robustness and minimal component count are critical.
Availability
LTC7852EUFD-1#PBF is available at Aetrix Electronics and suitable for AI accelerator VRMs, server CPU core power, and high-density telecom PSUs requiring stable component supply, long-term lifecycle assurance, and guaranteed -40°C to +125°C operation.
Supply support for LTC7852EUFD-1#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and computing markets since 1965.
The LTC7852EUFD-1#PBF belongs to Analog Devices' Power by Linear™ multiphase controller family, engineered specifically for high-efficiency, high-current DC/DC conversion in datacenter, AI, and telecom infrastructure where DrMOS integration, precision regulation, and thermal resilience are essential.
FAQ
What is the key functional difference between LTC7852EUFD-1#PBF and the standard LTC7852?
The LTC7852EUFD-1#PBF is the DrMOS-optimized variant: it replaces the dual DCR sense architecture (SNSN/SNSAVG pins) of the LTC7852 with an internal 1.5V SNSN bias rail for direct DrMOS current monitor interfacing. It uses a 36-pin QFN package versus the 48-pin GQFN of the base LTC7852, and omits IMON1/IMON2 and V1P5 pins. This makes LTC7852EUFD-1#PBF incompatible with discrete MOSFET or power block topologies - it is strictly for DrMOS-based designs.
Can LTC7852EUFD-1#PBF be used in a single-output, 6-phase configuration?
Yes, LTC7852EUFD-1#PBF supports single-output 6-phase operation by floating the PHCFG pin and externally connecting the ITH, VOSNS+, VOSNS–, RUN, ILIM, and SS pins between both outputs. This configures both channels identically, effectively doubling phase count on one output rail. The datasheet confirms this in the "Multiphase Operation" section and Figure 1c (6-phase mode). Ensure matched trace lengths and identical external components for balanced current sharing.
What is the purpose of the SNSN pins on LTC7852EUFD-1#PBF, and how should they be connected?
The SNSN pins (Pins 2 and 25) on LTC7852EUFD-1#PBF provide an internal 1.5V bias voltage for DrMOS current monitor outputs. They must be connected directly to the SNSN (sense negative) terminals of all six DrMOS devices - no external resistors or capacitors. This 1.5V rail establishes the common-mode reference for the differential SNSP signals, enabling accurate current measurement without DCR sense networks. Do not connect SNSN to ground or leave unconnected.
Does LTC7852EUFD-1#PBF support external clock synchronization, and what are the requirements?
Yes, LTC7852EUFD-1#PBF supports external clock synchronization via the PLLIN pin (Pin 1). It accepts a clean CMOS/TTL clock signal from 250kHz to 1.2MHz. The internal PLL locks with <1° phase jitter and automatically adjusts internal oscillator timing to align the rising edge of PWM1 with the PLLIN input. No external loop filter components are needed - the compensation network is fully integrated. CLKOUT can then drive PLLIN of downstream controllers for deterministic multichip phase alignment.
What is the minimum soft-start capacitor value required for LTC7852EUFD-1#PBF, and why is it specified?
The minimum soft-start capacitor for LTC7852EUFD-1#PBF is 22nF, connected from SS1 or SS2 to GND. This value ensures the internal 5µA pull-up current generates a linear 0–0.5V ramp within safe timing margins, allowing controlled VOUT slew rates and preventing inrush current overshoot. Using less than 22nF risks incomplete soft-start initialization, potentially causing PGOOD false trips or erratic startup behavior under pre-biased load conditions - as documented in the "Shutdown and Start-Up" section of the datasheet.
LTC7852EUFD-1#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 36-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Number of Outputs:
- 2
- Output Phases:
- 6
- Voltage - Supply (Vcc/Vdd):
- 4.5V ~ 5.5V
- Frequency - Switching:
- 200kHz ~ 1.2MHz
- Duty Cycle (Max):
- -
- Synchronous Rectifier:
- Yes
- Clock Sync:
- No
- Serial Interfaces:
- -
- Control Features:
- Current Limit, Enable, Frequency Control, Power Good, Ramp, Soft Start, Tracking
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 36-QFN (4x5)
LTC7852EUFD-1#PBF FAQ
1.How can I place an order for LTC7852EUFD-1#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC7852EUFD-1#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC7852EUFD-1#PBF reliable?
The price and inventory of LTC7852EUFD-1#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC7852EUFD-1#PBF is usually 5 days.
3.What payment methods are accepted for LTC7852EUFD-1#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC7852EUFD-1#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC7852EUFD-1#PBF?
LTC7852EUFD-1#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC7852EUFD-1#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC7852EUFD-1#PBF?
For technical support, including LTC7852EUFD-1#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC7852EUFD-1#PBF requirements.
6.How does Aetrix verify that LTC7852EUFD-1#PBF is sourced from the original manufacturer or authorized distributors?
All LTC7852EUFD-1#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC7852EUFD-1#PBF meets industry standards.
7.What is the process for return or replacement of LTC7852EUFD-1#PBF?
All LTC7852EUFD-1#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC7852EUFD-1#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC7852EUFD-1#PBF part is unused and in its original packaging.
Return procedure for LTC7852EUFD-1#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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