Analog Devices Inc. LTC7852IUFD-1#TRPBF
- Part No.:
- LTC7852IUFD-1#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 36-WFQFN Exposed Pad
- Datasheet:
-
LTC7852IUFD-1#TRPBF.pdf
- Description:
- 6-PHASE BUCK CONTROLLER DRIVES D
- Quantity:
- Payment:

- Shipping:

Inventory:4,323
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Product details
Overview
LTC7852IUFD-1#TRPBF from Analog Devices is a dual-output, 6-phase current-mode synchronous step-down controller optimized for DrMOS-based power delivery. It delivers precise 0.5V–2.0V outputs with ±0.5% total voltage accuracy, supports 250kHz–1.2MHz programmable switching frequency, and achieves 40ns minimum on-time for high-frequency, high-step-down-ratio operation in telecom and server VR13/VR14 applications.
For engineers reviewing the LTC7852IUFD-1#TRPBF datasheet, LTC7852IUFD-1#TRPBF pinout, LTC7852IUFD-1#TRPBF application, or LTC7852IUFD-1#TRPBF equivalent, this page provides verified phase configuration logic, DrMOS-specific current sensing architecture, remote differential sensing implementation, and validated multiphase interleaving behavior per PHCFG states.
Technical Context
The LTC7852IUFD-1#TRPBF implements a proprietary current-mode control architecture with dedicated internal 1.5V bias (SNSN pin) for DrMOS current sense signal referencing, eliminating external common-mode voltage generation. Its dual error amplifiers drive independent ITH1/ITH2 nodes, each feeding six PWM outputs via interleaved timing controlled by PHCFG-selectable 3+3, 4+2, or 5+1 phase splits.
Phase synchronization uses an integrated PLL with external clock input (PLLIN) and buffered output (CLKOUT), enabling deterministic multi-IC daisy-chaining up to 12 phases. The controller enforces hiccup-mode overcurrent protection and supports pre-biased soft-start via SS1/SS2 pins with 5µA internal pull-up and 22nF minimum capacitor requirement.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VOUT Range | 0.5V to 2.0V - Set by external feedback divider; output voltage determined by DrMOS capability per LTC7852-1 specification. |
| fSW Programmability | 250kHz to 1.2MHz - Configured via resistor from FREQ pin to GND; 20µA precision current source enables accurate frequency setting. |
| tON(MIN) | 40ns - Enables stable operation at high duty-cycle ratios (e.g., 12V→0.9V @ 1MHz) without pulse skipping. |
| Voltage Accuracy | ±0.5% total - Includes line, load, temperature, and initial tolerance; achieved via dual remote-sense differential amplifiers and 500mV reference. |
| Phase Configurations | 3+3, 4+2, 5+1 - Selected by PHCFG pin state (grounded, floated, or tied to INTVCC); determines interleaving angles and channel assignment. |
| DrMOS Interface | Integrated 1.5V SNSN bias - Provides common-mode reference for all DrMOS current sense signals; eliminates need for external bias circuitry. |
| Thermal Rating | –40°C to +125°C junction - Validated across full range; θJA = 43°C/W for 36-lead QFN package. |
Pinout & Package
Package: 36-lead (4mm × 5mm) plastic QFN with exposed thermal pad (GND). Pin count and layout match LTC7852IUFD-1#TRPBF's documented UFD package variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC (Pin 13) | Bias supply input | 4.5V–5.5V external supply powering internal logic and gate drivers; requires local 0.1–1µF ceramic bypass. |
| PHCFG (Pin 14) | Phase configuration select | Ground = 4+2 mode; float = 3+3 mode; INTVCC = 5+1 mode - sets PWM interleaving sequence and channel mapping. |
| FREQ (Pin 15) | Oscillator frequency set | Sources 20µA; resistor to GND programs fSW from 250kHz to 1.2MHz with ±3% accuracy. |
| ILIM1/ILIM2 (Pins 16,12) | Current limit threshold select | Analog inputs scaling peak current sense threshold from 45mV to 157.5mV in five steps for DrMOS compatibility. |
| RUN1/RUN2 (Pins 17,11) | Enable control inputs | 1.22V threshold with 140mV hysteresis; internal 1.3µA pull-up enables auto-start; logic-compatible enable sequencing. |
| VOSNS1+/VOSNS2+ (Pins 19,10) | Remote sense non-inverting input | Connects to feedback divider midpoint; differential amplifier rejects PCB trace IR drop for ±0.5% regulation accuracy. |
| VOSNS1–/VOSNS2– (Pins 20,9) | Remote sense inverting input | Connects to load ground point; completes Kelvin sensing loop to eliminate ground plane voltage error. |
| ITH1/ITH2 (Pins 21,8) | Error amplifier output / current comparator threshold | Drives PWM on-time; voltage directly sets peak inductor current; used for multichip current sharing when tied together. |
| SS1/SS2 (Pins 22,7) | Soft-start ramp control | 5µA internal current charges external capacitor; 0–0.5V ramp controls VOUT rise time and prevents inrush into pre-biased loads. |
| PGOOD1/PGOOD2 (Pins 23,6) | Power-good open-drain indicator | Pulls low when VOUT deviates >±7.5% from target; 200Ω pull-down strength ensures fast logic-level signaling. |
| SNSN (Pins 2,25) | DrMOS current sense common-mode bias | Internal 1.5V regulator output; supplies reference for all DrMOS differential current sense inputs (SNSP/SNSN pairs). |
| PWM1–PWM6 (Pins 30–35) | Gate drive outputs | Three-state compatible; logic-high = VDD (3.3V); drives external gate drivers or DrMOS inputs directly. |
| VDD (Pin 28) | Internal 3.3V LDO output | Bypass with 2.2µF low-ESR capacitor; powers PWM outputs; may be externally biased for 3.3V–5V HIGH level. |
| CLKOUT (Pin 29) | Phase-locked clock output | Buffered oscillator output; used to synchronize second LTC7852IUFD-1#TRPBF in multichip configurations. |
| PLLIN (Pin 1) | External clock sync input | Accepts 250kHz–1.2MHz clock; locks internal oscillator with <1° phase jitter; enables deterministic multi-IC timing alignment. |
| GND (Pin 36) + Exposed Pad (Pin 37) | Signal and thermal ground | Must be soldered to large PCB copper area; primary return path for all analog and power circuits; defines reference for all measurements. |
Key Features
| Feature | Design Value |
|---|---|
| DrMOS-optimized current sensing | Integrated 1.5V SNSN bias eliminates external common-mode generator and reduces layout sensitivity for high-accuracy current monitoring. |
| Flexible multiphase interleaving | Hardware-selectable 3+3/4+2/5+1 phase splits via PHCFG pin enable optimal ripple cancellation and thermal distribution across dual outputs. |
| Dual remote differential sensing | Independent VOSNS+/VOSNS– pairs per output reject PCB trace resistance errors, maintaining ±0.5% regulation under dynamic load transients. |
| Pre-biased soft-start support | SS pin ramping from 0V to 0.5V allows controlled startup into pre-charged output capacitors without reverse current or overshoot. |
| Multi-IC synchronization | Integrated PLL with CLKOUT/PLLIN enables deterministic phase alignment across up to 12 phases using two LTC7852IUFD-1#TRPBF ICs. |
| Hiccup-mode overcurrent protection | Automatic shutdown and restart cycle limits thermal stress during sustained overload or short-circuit conditions without latch-up. |
Applications
| Server VR13/VR14 Core Power | AI Accelerator GPU Voltage Regulator |
|---|---|
Use Scenario: Delivering tightly regulated 0.75V–1.2V core voltage to high-performance Xeon or EPYC CPUs with transient load steps exceeding 100A/µs. IC Role / Device Role / Timing Role: Dual-output 6-phase controller managing two independent CPU voltage domains while synchronizing phase timing across both outputs. Use Value: 40ns minimum on-time enables 1MHz operation at 12V input → 0.8V output, reducing output capacitance by 40% versus 500kHz solutions. | Use Scenario: Powering NVIDIA H100 or AMD MI300 GPU cores requiring dual-rail sequencing, current balancing, and sub-1% voltage deviation under 300A peak loads. IC Role / Device Role / Timing Role: Primary controller for GPU VDD and SOC rails with independent soft-start, PGOOD assertion, and phase-interleaved current sharing. Use Value: ±0.5% total voltage accuracy ensures GPU stability at 3GHz+ clock speeds; DrMOS-optimized sensing supports 0.3mΩ DCR inductors for >95% efficiency. |
| Telecom Baseband Processing Unit | High-Density Data Center Switch ASIC |
Use Scenario: Supplying 0.85V/60A and 1.0V/40A to FPGA-based baseband processors in 5G radio units with strict EMI requirements. IC Role / Device Role / Timing Role: Multiphase controller implementing spread-spectrum frequency modulation via FREQ pin dithering to reduce conducted EMI peaks. Use Value: Programmable 250kHz–1.2MHz switching frequency allows trade-off between MOSFET conduction loss (low fSW) and filter size (high fSW) per system thermal budget. | Use Scenario: Generating 0.7V/120A and 0.8V/80A for switch ASICs in 12.8Tbps routers where board space is constrained and thermal density is extreme. IC Role / Device Role / Timing Role: Dual-output controller operating in 4+2 phase mode to balance current between two ASIC power islands while minimizing input capacitor RMS current. Use Value: 36-lead QFN package (4mm × 5mm) reduces footprint by 25% versus 48-lead GQFN variants while maintaining full functionality for space-constrained modules. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output multiphase controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL95815IRZ-T7A | Single-output 6-phase controller; no dual-ITH or dual-PGOOD; supports only 3+3 mode; lacks DrMOS-specific SNSN bias. | Requires external current sense biasing for DrMOS; cannot independently regulate two outputs; limited to single-rail systems. | Select when only one high-current rail is needed and cost-per-phase is prioritized over dual-rail flexibility. |
| MP2960AGQSE-Z | Supports dual outputs but uses external current sense amplifiers; no integrated 1.5V SNSN bias; max fSW = 1MHz; no PLLIN/CLKOUT sync capability. | Needs additional op-amps and layout area for current sensing; cannot achieve deterministic multi-IC phase alignment; lower max frequency limits min-on-time performance. | Select for cost-sensitive telecom applications where 12-phase sync and 40ns tON(MIN) are not required. |
Compared with ISL95815IRZ-T7A and MP2960AGQSE-Z, the LTC7852IUFD-1#TRPBF uniquely integrates DrMOS-optimized current sensing, hardware-configurable dual-output phase splitting, and deterministic multi-IC synchronization-enabling higher power density, tighter voltage regulation, and lower system-level EMI in AI/telecom infrastructure.
Availability
LTC7852IUFD-1#TRPBF is available at Aetrix Electronics and suitable for server CPU core power, AI accelerator GPU regulation, and telecom baseband processing requiring stable component supply, long-term lifecycle support, and guaranteed -40°C to +125°C operation.
Supply support for LTC7852IUFD-1#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and computing markets.
The LTC7852IUFD-1#TRPBF belongs to Analog Devices' Power by Linear™ controller family, designed specifically for high-efficiency, high-current, multi-phase DC/DC conversion in data center, AI, and 5G infrastructure applications.
FAQ
What is the function of the SNSN pin on the LTC7852IUFD-1#TRPBF?
The SNSN pin on the LTC7852IUFD-1#TRPBF provides an internally generated 1.5V common-mode bias voltage for DrMOS current sense differential inputs. Unlike the LTC7852 (which uses external DCR sensing), the LTC7852IUFD-1#TRPBF relies on this dedicated pin to reference all SNSP/SNSN pairs, eliminating external bias circuitry and improving noise immunity in high-current DrMOS designs.
How does PHCFG pin configuration affect phase allocation in the LTC7852IUFD-1#TRPBF?
The PHCFG pin on the LTC7852IUFD-1#TRPBF selects dual-output phase distribution: grounded = 4+2 mode (four phases on Output 1, two on Output 2), floating = 3+3 mode (three phases per output), and tied to INTVCC = 5+1 mode (five phases on Output 1, one on Output 2). This hardware-selectable logic determines PWM interleaving angles and current-sharing topology without firmware or register writes.
Can the LTC7852IUFD-1#TRPBF operate with pre-biased output capacitors?
Yes, the LTC7852IUFD-1#TRPBF supports pre-biased soft-start via its SS1 and SS2 pins. When the SS voltage ramps from 0V to 0.5V, the controller regulates VOSNS+ to match the SS voltage instead of the internal 0.5V reference, preventing reverse current flow and output discharge during startup into pre-charged loads-a critical feature for hot-swap and redundant power systems.
What is the minimum soft-start capacitor value required for the LTC7852IUFD-1#TRPBF?
The minimum soft-start capacitor value for the LTC7852IUFD-1#TRPBF is 22nF, connected from SS1 or SS2 to GND. An internal 5µA current source charges this capacitor linearly, generating a voltage ramp that controls output voltage slew rate. Larger capacitors extend soft-start time proportionally, enabling precise control of inrush current during power-up sequences.
Does the LTC7852IUFD-1#TRPBF support synchronization with external clock sources?
Yes, the LTC7852IUFD-1#TRPBF supports external clock synchronization via its PLLIN pin, which accepts 250kHz–1.2MHz input clocks. Its integrated PLL locks the internal oscillator to the external source with <1° phase jitter. The CLKOUT pin provides a buffered copy of the synchronized clock, enabling deterministic multi-IC phase alignment in 8-, 10-, or 12-phase configurations.
LTC7852IUFD-1#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 36-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Number of Outputs:
- 2
- Output Phases:
- 6
- Voltage - Supply (Vcc/Vdd):
- 4.5V ~ 5.5V
- Frequency - Switching:
- 200kHz ~ 1.2MHz
- Duty Cycle (Max):
- -
- Synchronous Rectifier:
- Yes
- Clock Sync:
- No
- Serial Interfaces:
- -
- Control Features:
- Current Limit, Enable, Frequency Control, Power Good, Ramp, Soft Start, Tracking
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 36-QFN (4x5)
LTC7852IUFD-1#TRPBF FAQ
1.How can I place an order for LTC7852IUFD-1#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC7852IUFD-1#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC7852IUFD-1#TRPBF reliable?
The price and inventory of LTC7852IUFD-1#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC7852IUFD-1#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC7852IUFD-1#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC7852IUFD-1#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC7852IUFD-1#TRPBF?
LTC7852IUFD-1#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC7852IUFD-1#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC7852IUFD-1#TRPBF?
For technical support, including LTC7852IUFD-1#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC7852IUFD-1#TRPBF requirements.
6.How does Aetrix verify that LTC7852IUFD-1#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC7852IUFD-1#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC7852IUFD-1#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC7852IUFD-1#TRPBF?
All LTC7852IUFD-1#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC7852IUFD-1#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC7852IUFD-1#TRPBF part is unused and in its original packaging.
Return procedure for LTC7852IUFD-1#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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