Analog Devices Inc. LTM2893CY#PBF
- Part No.:
- LTM2893CY#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Digital Isolators
- Package:
- 36-BGA
- Datasheet:
-
LTM2893CY#PBF.pdf
- Description:
- DGTL ISOL 6000VRMS 9CH SPI 36BGA
- Quantity:
- Payment:

- Shipping:

Inventory:117
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTM2893CY#PBF from Analog Devices is a high-speed isolated μModule SPI interface IC optimized for 1Msps, 18-bit SAR ADCs (e.g., LTC2338), providing galvanic isolation of conversion start (CNV→CNV2), busy signaling, and three multiplexer select lines with 30psRMS aperture jitter and 20ns latency. It supports 100MHz SPI I/O, 8–32-bit word lengths, and operates across 1.71V–5.5V logic supplies on both sides.
For engineers reviewing the LTM2893CY#PBF datasheet, LTM2893CY#PBF pinout, LTM2893CY#PBF application, or LTM2893CY#PBF equivalent, key selection criteria include its 6000VRMS isolation rating, low-latency CNV propagation, configurable SPI timing for simultaneous-sampling ADCs, and BGA package compatibility with high-density industrial data acquisition layouts.
Technical Context
The LTM2893CY#PBF implements transformer-based digital isolation using coreless µModule technology, encoding logic-side signals into differential pulses across an integrated isolation barrier with error checking and fail-safe shutdown. Its dual-state machine architecture separately manages ADC read cycles (CNV→BUSY2→MISOA2→MISOA) and optional configuration register access via CSC.
It delivers deterministic timing: CNV→CNV2 delay is 12–33ns (typ. 21ns), aperture jitter is 30psRMS, and SCK2 output period is 10ns at 100MHz. The device supports independent supply domains (VL/VL2 = 1.71–5.5V; VCC/VCC2 = 3.0–5.5V) and tolerates >50kV/µs common-mode transients while maintaining uninterrupted communication.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Rating | 6000VRMS for 1 minute - enables reinforced insulation per UL 1577 and CSA 60601-1 (2 MOPP) in medical and industrial safety-critical systems. |
| CNV→CNV2 Aperture Jitter | 30psRMS - preserves SNR >95dB in 18-bit ADC systems (e.g., LTC2328-18) by minimizing sampling time uncertainty. |
| SPI Data Rate | 100MHz SCK/SCK2 - supports 1Msps throughput with zero-cycle latency for real-time high-speed data acquisition. |
| Logic Supply Range | VL/VL2 = 1.71V to 5.5V - interoperates with FPGA, MCU, or ASIC I/O banks across 1.8V, 3.3V, and 5V domains without level shifters. |
| Package Dimensions | 15mm × 6.25mm × 2.06mm BGA - compact footprint suitable for space-constrained PCB layouts in test equipment and process controllers. |
| Operating Temperature | 0°C to 70°C (C-grade) - validated for commercial and industrial ambient environments without derating. |
| Common-Mode Immunity | >50kV/µs - ensures robust operation in noisy motor drives or power electronics where ground differentials exceed 1kV. |
Pinout & Package
36-pin BGA (15mm × 6.25mm × 2.06mm), RoHS-compliant SAC305 ball finish, MSL Level 3. Pin mapping validated per Analog Devices LTM2893 Rev C datasheet (pages 8–9).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CNV (A6) | Conversion Start Input | Rising edge triggers isolated CNV2 with 21ns typ. delay and 30psRMS jitter - critical for precise sampling timing in SAR ADCs. |
| BUSY (A5) | ADC Busy Status Output | High indicates ongoing conversion; falling edge signals valid data ready in MISOA/MISOB buffers - synchronizes host read timing. |
| SA/SB/SC (C4–C6) | Isolated Multiplexer Select Inputs | Pass-through control signals to SA2/SB2/SC2 (N4–N6) - enables analog channel/gain switching synchronized with ADC sampling. |
| MISOA/MISOB (B2–B3) | Isolated SPI Data Outputs | Deliver ADC result bits from MISOA2/MISOB2 after BUSY2 fall - support dual-data-stream readout for interleaved or differential ADCs. |
| ON (A1) | Logic-Side Enable Input | Active-high control of MOSI/SCK/CNV/MISOA/MISOB drivers - allows power-gated operation and fault recovery without reset. |
| VCC/VCC2 (C1/N1) | Primary/Isolated Power Supplies | 3.0–5.5V domains power internal isolators and buffers - decoupling with 1µF ceramic required per supply pin per datasheet layout guidelines. |
Key Features
| Feature | Design Value |
|---|---|
| Transformer-Based Isolation | Coreless µModule barrier provides 6000VRMS withstand, 50kV/µs CMTI, and <3pF input-to-output capacitance - eliminates optocoupler latency and aging drift. |
| Configurable SPI Interface | 8–32-bit word length, selectable SCK2 frequency (up to 100MHz), and CRC enable/disable - adapts to diverse ADC families (LTC23xx, LTC234x) without firmware changes. |
| Dual-Mode ADC Support | Read-only mode (LTM2893) for standard SAR ADCs; read/write mode (LTM2893-1 variant) for simultaneous-sampling ADCs requiring configuration writes - same pinout, software-selectable. |
| Three Isolated Select Lines | SA/SB/SC → SA2/SB2/SC2 pass-through with 40–150ns propagation delay - enables synchronized analog front-end control (e.g., mux/gain) aligned to CNV timing. |
| Fault Detection & Recovery | Open-drain FAULT (B6) asserts on SPI buffer under-run, invalid CSC/SS framing, or isolation barrier errors - enables system-level diagnostics and safe shutdown. |
Applications
| Industrial Process Control | Test and Measurement Equipment |
|---|---|
|
Use Scenario: Isolating 18-bit ADCs in PLC analog input modules measuring ±10V sensor signals in 4–20mA loop-powered field devices. IC Role / Device Role / Timing Role: LTM2893CY#PBF acts as the isolated SPI bridge between FPGA controller and LTC2338 ADC, transferring CNV with 30psRMS jitter to maintain 95dB SNR under EMI-rich factory floor conditions. Use Value: Enables direct connection to high-voltage field buses without external level shifters or optocouplers, reducing BOM count and improving long-term reliability. |
Use Scenario: High-speed digitizer card acquiring transient waveforms from oscilloscope front-ends with simultaneous multi-channel sampling. IC Role / Device Role / Timing Role: LTM2893CY#PBF interfaces FPGA to LTC2348 ADC, managing dual SPI transactions (read result + write config) with sub-100ns total latency for 2Msps aggregate throughput. Use Value: Eliminates timing skew between channels caused by discrete isolators, ensuring true simultaneous sampling across 8+ channels. |
| Medical Imaging Signal Chain | Energy Metering with Anti-Tampering |
|
Use Scenario: Isolating precision ADCs in ultrasound beamformer receive paths where signal integrity and low noise are critical. IC Role / Device Role / Timing Role: LTM2893CY#PBF isolates LTC2378-18 ADC outputs while preserving 100dB SNR performance up to 1MHz input frequency via ultra-low-jitter CNV2 timing. Use Value: Meets IEC 60601-1 2-MOPP safety requirements without compromising dynamic range or introducing clock-induced artifacts. |
Use Scenario: Smart electricity meter ADC isolation to prevent high-voltage surges (e.g., lightning strikes) from propagating to microcontroller side. IC Role / Device Role / Timing Role: LTM2893CY#PBF provides 6000VRMS isolation between metrology ADC (LTC2328-18) and energy processing SoC, with fault detection flagging isolation barrier degradation. Use Value: Achieves EN 50470-3 surge immunity compliance while enabling real-time harmonic analysis at 1Msps without latency penalties. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed isolated SPI interface applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM6401ARWZ | Quad-channel 25Mbps iCoupler isolator with integrated DC/DC; no native SPI protocol handling or CNV jitter optimization. | Requires external logic to manage ADC timing sequences; unsuitable for sub-50ps aperture jitter requirements. | Select only when full custom SPI state machine implementation is acceptable and jitter tolerance >100ps. |
| ISO6741QDWR | Quad-channel 50Mbps capacitive isolator; no integrated SPI buffer, configuration register, or select signal pass-through. | Needs external FPGA logic for BUSY/CNV synchronization and lacks SA/SB/SC routing - increases design complexity and PCB area. | Choose for cost-sensitive, lower-speed (<50Msps) isolation where protocol offload is handled elsewhere. |
Compared with ADUM6401ARWZ and ISO6741QDWR, the LTM2893CY#PBF uniquely integrates ADC-specific timing control, ultra-low-jitter conversion triggering, and three dedicated isolated select lines in a single BGA package - eliminating external glue logic and guaranteeing sub-100ns end-to-end latency for 1Msps 18-bit acquisition.
Availability
LTM2893CY#PBF is available at Aetrix Electronics and suitable for industrial process control, test and measurement equipment, and medical imaging systems requiring stable component supply, long-term lifecycle assurance, and certified 6000VRMS isolation.
Supply support for LTM2893CY#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTM2893CY#PBF belongs to Analog Devices' µModule isolated interface product line, designed specifically to simplify high-fidelity, safety-certified ADC interfacing in noise-immune, space-constrained systems without sacrificing speed or precision.
FAQ
What is the maximum SPI clock frequency supported by the LTM2893CY#PBF?
The LTM2893CY#PBF supports up to 100MHz SCK/SCK2 operation, enabling 1Msps throughput with zero-cycle latency. At this rate, SCK2 period is 10ns (min 9.5ns), and timing parameters like tSCK2H/tSCK2L are guaranteed ≥4ns. Performance is validated across the full 0°C to 70°C temperature range with 20pF load.
Does the LTM2893CY#PBF support simultaneous-sampling ADCs like the LTC2348?
No - the LTM2893CY#PBF is the read-only variant optimized for ADCs such as LTC2338 and LTC2328. For simultaneous-sampling ADCs requiring configuration writes (e.g., LTC2348), the LTM2893CY-1#PBF variant must be used. Both share identical pinout and package but differ in internal firmware and CSC register functionality.
How does the LTM2893CY#PBF achieve 30psRMS aperture jitter on CNV→CNV2?
The LTM2893CY#PBF achieves 30psRMS aperture jitter through transformer-based µModule isolation with precision edge-detection circuitry and matched propagation paths. This is measured directly on CNV2 output under 1.71–5.5V VL/VL2 conditions and is critical for preserving SNR in 18-bit SAR ADCs like LTC2328-18.
What safety certifications apply to the LTM2893CY#PBF?
The LTM2893CY#PBF is UL 1577 certified (File #255632) for 6000VRMS isolation, CSA certified to IEC/UL 60950-1 and 62368-1 (reinforced insulation), and meets IEC 60601-1 for two means of patient protection (2 MOPP) at 287.5VRMS - verified per datasheet Rev C regulatory section.
Can the LTM2893CY#PBF operate with 1.8V logic supplies on both sides?
Yes - the LTM2893CY#PBF supports VL and VL2 from 1.71V to 5.5V, including 1.8V operation. Input thresholds scale as 0.2×VL/0.8×VL, and output drive strength (VOH/VOL) is specified down to 1.71V. Full 100MHz timing compliance is maintained at 1.8V with 20pF load per datasheet Electrical Characteristics table.
LTM2893CY#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 36-BGA
- Packaging:
- Tray
- Product Status:
- Active
- Technology:
- Magnetic Coupling
- Type:
- SPI
- Isolated Power:
- No
- Number of Channels:
- 9
- Inputs - Side 1/Side 2:
- 6/6
- Channel Type:
- Bidirectional, Unidirectional
- Voltage - Isolation:
- 6000Vrms
- Common Mode Transient Immunity (Min):
- 50kV/µs
- Data Rate:
- 100Mbps
- Propagation Delay tpLH / tpHL (Max):
- 150ns, 150ns
- Pulse Width Distortion (Max):
- -
- Rise / Fall Time (Typ):
- 10ns, 10ns
- Voltage - Supply:
- 3V ~ 5.5V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 36-BGA (15x6.25)
LTM2893CY#PBF FAQ
1.How can I place an order for LTM2893CY#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTM2893CY#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTM2893CY#PBF reliable?
The price and inventory of LTM2893CY#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTM2893CY#PBF is usually 5 days.
3.What payment methods are accepted for LTM2893CY#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTM2893CY#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTM2893CY#PBF?
LTM2893CY#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTM2893CY#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTM2893CY#PBF?
For technical support, including LTM2893CY#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTM2893CY#PBF requirements.
6.How does Aetrix verify that LTM2893CY#PBF is sourced from the original manufacturer or authorized distributors?
All LTM2893CY#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTM2893CY#PBF meets industry standards.
7.What is the process for return or replacement of LTM2893CY#PBF?
All LTM2893CY#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTM2893CY#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTM2893CY#PBF part is unused and in its original packaging.
Return procedure for LTM2893CY#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTM2893CY#PBF Tags
-
ISO1212DBQR
Texas Instruments

-
ISO6721BDR
Texas Instruments

-
SI8710AC-B-ISR
Skyworks Solutions Inc.

-
ISO7720FDR
Texas Instruments

-
ISO7721DR
Texas Instruments

-
ISO7721FDR
Texas Instruments

-
SI8710CC-B-ISR
Skyworks Solutions Inc.

-
ISO6741FQDWRQ1
Texas Instruments

-
ISO7721DWVR
Texas Instruments
-
ISO7762FDBQR
Texas Instruments

-
ISO7741DWR
Texas Instruments

-
ISO7741FDWR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

