Analog Devices Inc. LTM2893HY#PBF

Overview

LTM2893HY#PBF from Analog Devices is a high-speed isolated μModule SPI interface IC optimized for 1Msps, 18-bit SAR ADCs (e.g., LTC2338), providing galvanic isolation of conversion start (CNV→CNV2), busy signaling, and three multiplexer select lines with 30ps RMS aperture jitter and 20ns latency. It supports 100MHz SPI I/O, 8–32-bit word lengths, and operates across –40°C to +125°C in industrial and test equipment.

For engineers reviewing the LTM2893HY#PBF datasheet, LTM2893HY#PBF pinout, LTM2893HY#PBF application, or LTM2893HY#PBF equivalent, key selection criteria include its 6000VRMS isolation rating, low-jitter CNV propagation, configurable logic-level compatibility (1.71V–5.5V), and support for simultaneous-sampling ADC control via isolated SCK2/SS2/MOSI2 on the H-grade BGA package.

Technical Context

The LTM2893HY#PBF implements coreless transformer-based digital isolation with integrated SPI buffer state machines, enabling cycle-accurate, zero-latency-throughput communication between FPGA/microcontroller hosts and isolated ADCs. Its dual-domain architecture separates logic-side (VL/GND) and isolated-side (VL2/GND2) power domains while maintaining precise timing alignment between CNV and CNV2.

It features independent configuration via CSC-controlled register for SCK2 frequency (up to 100MHz), SPI word length, device count, and select signal direction-critical for matching timing constraints of SAR ADCs like LTC2328-18 and LTC2348. The μModule integrates isolation barrier, SPI transceivers, and control logic in a single 15mm × 6.25mm BGA.

Key Specifications

Pinout & Package

36-pin BGA (15mm × 6.25mm × 2.06mm), RoHS-compliant SAC305 ball finish, MSL Level 3. Thermal resistance θJA = 36°C/W; θJB = 19.1°C/W. Top-side marking: "LTM2893Y".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ADC isolation applications.

Compared with ADUM6401ARWZ and ISO7841FDWW, the LTM2893HY#PBF delivers integrated ADC interface logic, sub-30ps CNV jitter, and synchronized select signal routing - reducing BOM count, PCB area, and firmware complexity in high-fidelity data acquisition systems.

Availability

LTM2893HY#PBF is available at Aetrix Electronics and suitable for industrial process control, test and measurement equipment, and motor drive current sensing requiring stable component supply across extended temperature ranges and high-reliability isolation.

Supply support for LTM2893HY#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, industrial automation, and communications markets.

The LTM2893HY#PBF belongs to Analog Devices' μModule isolated interface product line, designed specifically to simplify high-speed, high-accuracy ADC isolation in space-constrained, noise-sensitive applications without sacrificing timing integrity.

FAQ

What is the maximum SPI clock frequency supported by the LTM2893HY#PBF?

The LTM2893HY#PBF supports an isolated SCK2 output frequency up to 100MHz, enabling 1Msps throughput with zero-cycle latency. This is confirmed in the Switching Characteristics table (tSCK2 = 9.5–10.8ns period) and applies across the full –40°C to +125°C operating range. The LTM2893HY#PBF achieves this using coreless transformer isolation and integrated SPI buffering, eliminating the need for external clock conditioning.

Does the LTM2893HY#PBF support write operations to the ADC, or is it read-only?

The LTM2893HY#PBF is a read-only interface variant - it supports reading ADC results via MISOA2/MISOB2 and driving CNV2, BUSY2, SS2, and SCK2, but does not implement MOSI2-driven write functionality. This distinguishes it from the LTM2893-1 family (e.g., LTM2893HY-1#PBF), which adds configuration register access and ADC command writes. For LTM2893HY#PBF, MOSI2 must be tied to GND2.

What is the aperture jitter specification of the LTM2893HY#PBF, and why does it matter for ADC performance?

The LTM2893HY#PBF specifies 30ps RMS aperture jitter on the CNV→CNV2 path. This directly limits achievable SNR in high-resolution SAR ADC systems: for an 18-bit converter sampling at 1Msps, 30ps jitter contributes ≤0.5 LSB of noise, preserving >95dB measured SNR (as verified with LTC2328-18). Lower jitter would yield marginal improvement; higher jitter degrades effective resolution nonlinearly.

Can the LTM2893HY#PBF operate with 1.8V logic levels on both sides?

Yes - the LTM2893HY#PBF supports VL and VL2 supply voltages from 1.71V to 5.5V independently, including 1.8V operation. Input thresholds scale as 0.2×VL/0.8×VL (and same for VL2), and output drive strength remains functional at 1.8V (VOH ≥ 1.6V, VOL ≤ 0.2V at 500µA load). This is validated across temperature and documented in the Electrical Characteristics table.

How does the LTM2893HY#PBF handle multiple ADCs in parallel configurations?

The LTM2893HY#PBF supports multi-ADC systems via the BUSYS input (P6), which accepts a secondary ADC's BUSY signal. When asserted, it extends the isolated-side read window to accommodate staggered conversions. The device does not natively support daisy-chained SPI - each ADC requires its own LTM2893HY#PBF or a multiplexed bus architecture managed externally. Pin SA/SB/SC can coordinate analog mux selection across channels.