Analog Devices Inc. LTM2895IY#PBF
- Part No.:
- LTM2895IY#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Digital Isolators
- Package:
- 36-BGA
- Datasheet:
-
LTM2895IY#PBF.pdf
- Description:
- DGTL ISOL 6000VRMS 9CH SPI 36BGA
- Quantity:
- Payment:

- Shipping:

Inventory:100
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Product details
Overview
LTM2895IY#PBF from Analog Devices (formerly Linear Technology) is a galvanically isolated µModule SPI transceiver with integrated DAC control signaling, designed to isolate LTC/LTC-compatible general-purpose DACs (e.g., LTC2642-16) and generic SPI peripherals. It delivers 100MHz SPI-compatible I/O, supports 8–32-bit configurable word length, provides three isolated select signals (SA2/SB2/SC2), and maintains 6000VRMS isolation for 1 minute - enabling robust noise suppression in industrial process control and test equipment.
For engineers reviewing the LTM2895IY#PBF datasheet, LTM2895IY#PBF pinout, LTM2895IY#PBF application, or LTM2895IY#PBF equivalent, key selection criteria include its 100MHz isolated SCK2 timing, falling-edge-sensitive low-jitter LOAD2 output (≤33ps RMS jitter), dual isolated chip selects (SS2/SSB2), 1.71V–5.5V logic supply flexibility, and CSA/UL/IEC-reinforced insulation compliance for safety-critical embedded systems.
Technical Context
The LTM2895IY#PBF implements transformer-based isolator µModule technology with differential pulse encoding across a coreless transformer barrier, supporting bidirectional SPI signal translation while maintaining high common-mode transient immunity (>50kV/µs). It operates as an SPI slave on the logic side and an SPI master on the isolated side, recreating only essential edges (SCK, SS, LOAD) across the barrier.
Its architecture includes configuration registers (0x30H/0x83H) that set SCK2 frequency (100/66/50/40/33/25/20/10MHz) and word length (8–32 bits), enabling precise timing alignment with target DACs or SPI slaves. The LOAD→LOAD2 path uses dedicated low-jitter circuitry independent of SPI data flow, delivering sub-35ns aperture delay and ≤33ps RMS jitter for synchronized DAC updates.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Rating | 6000VRMS for 1 minute (UL 1577); reinforced insulation per IEC 62368-1 at 455VRMS |
| SPI Data Rate | Up to 100MHz SCK2 output; supports 50MHz logic-side SCK with 1.5ns MOSI setup time |
| LOAD2 Jitter | ≤33ps RMS; enables precise LDAC timing for high-resolution DACs like LTC2642-16 |
| Logic Supply Range | 1.71V–5.5V (VL), enabling direct interface with 1.8V/2.5V/3.3V/5V microcontrollers |
| Operating Temp | –40°C to +85°C (I-grade), qualified for industrial automation and test instrumentation |
| Package | 36-ball BGA, 15mm × 6.25mm × 2.06mm, RoHS-compliant SAC305 finish |
| Common-Mode Immunity | ≥50kV/µs transient rejection between GND and GND2, critical for noisy motor drives |
Pinout & Package
36-ball BGA package (15mm × 6.25mm × 2.06mm) with 0.8mm ball pitch; top-side marking "LTM2895Y"; moisture sensitivity level (MSL) 3; requires controlled reflow per Linear/BGA-assy guidelines.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ON (A1) | Logic-side enable input | Active-high reset control; must be pulled high to activate logic-side interface |
| SS (A2) | Primary slave select input | Low-true framing signal for SPI transactions; weak internal pull-up to VL |
| MOSI (A3) | Serial data input (logic side) | Carries configuration register writes and DAC command data; requires external pull-down if floating |
| SCK (A4) | Serial clock input (logic side) | Rising-edge sampled; timing referenced to VL; weak pull-down recommended |
| BUSY (A5) | Startup status indicator | High during power-up initialization; goes low when isolated side is ready |
| LOAD (A6) | DAC load trigger input | Falling-edge sensitive; initiates low-jitter LOAD2 pulse for synchronous DAC update |
| VL (B1) | Logic interface supply | 1.71V–5.5V reference for all logic-side I/O; internally bypassed with 1µF capacitor |
| MISO (B2) | Serial data output (logic side) | Read-back data from MISO2; high-impedance when SS is high; requires external pull-up/down |
| SSB (B4) | Secondary chip select/config input | Enables configuration register access or second DAC channel; weak pull-up to VL |
| FAULT (B6) | Open-drain fault indicator | Active-low signal reporting communication errors or data corruption; requires 10kΩ pull-up to VL |
| VCC (C1) | Main supply voltage | 3.0V–5.5V analog supply; internally bypassed with 1µF capacitor |
| SA/SB/SC (C4–C6) | Configurable select pass-through inputs | Control external multiplexers or PGAs; direction set via config register; weak pull-downs |
| VCC2 (N1) | Isolated supply voltage | 3.0V–5.5V supply for isolated-side circuitry; internally bypassed with 1µF capacitor |
| SA2/SB2/SC2 (N4–N6) | Isolated select outputs | Pass-through of SA/SB/SC with timing constraints; weak pull-downs; used for peripheral control |
| VL2 (P1) | Isolated interface supply | 1.71V–5.5V reference for isolated-side I/O; internally bypassed with 1µF capacitor |
| MISO2 (P2) | Isolated serial data input | Receives read-back data from DAC or SPI slave; high-impedance when SS2/SSB2 high |
| SSB2 (P4) | Secondary isolated chip select | Output for second DAC channel or SPI device; driven by internal logic |
| ON2 (R1) | Isolated-side enable | Active-high control for isolated interface; must be asserted before using isolated signals |
| SS2 (R2) | Primary isolated chip select | Drives slave select line of isolated DAC; synchronized with SCK2 and MOSI2 |
| MOSI2 (R3) | Isolated serial data output | Sends command data to DAC; edge-aligned to SCK2 falling edge (≤50MHz) or rising edge (≥66MHz) |
| SCK2 (R4) | Isolated serial clock output | Configurable 10–100MHz clock; low when SS2 is high; defines timing for isolated SPI bus |
| LOAD2 (R6) | Isolated DAC load output | Low-jitter LDAC signal; pulse width 40ns (≥40MHz SCK2) or 60ns (≤33MHz SCK2) |
Key Features
| Feature | Design Value |
|---|---|
| Transformer-based galvanic isolation | Eliminates ground loops and enables safe interfacing between disparate voltage domains (e.g., 24V PLC and 3.3V MCU) |
| Configurable SCK2 frequency & word length | Eight SCK2 options (10–100MHz) and eight word lengths (8–32 bits) allow precise matching to DAC timing requirements |
| Dual isolated chip selects (SS2/SSB2) | Supports two independent DAC channels or cascaded SPI peripherals without external logic |
| Three isolated select signals (SA2/SB2/SC2) | Enables control of external multiplexers, PGAs, or calibration switches directly from logic side |
| Low-jitter LOAD2 path | 33ps RMS jitter and 12–33ns LOAD→LOAD2 delay ensure deterministic DAC output updates for precision metrology |
| Integrated fault detection | Single open-drain FAULT pin reports communication errors, invalid inputs, or data corruption across isolation barrier |
Applications
| Industrial Process Control | Test & Measurement Equipment |
|---|---|
|
Use Scenario: Isolating 16-bit DAC outputs in programmable logic controller (PLC) analog output modules subject to 2kV surge transients. IC Role / Device Role / Timing Role: LTM2895IY#PBF acts as SPI-to-isolated-SPI bridge with LOAD2-synchronized LDAC strobing for simultaneous multi-channel DAC updates. Use Value: 6000VRMS isolation withstands industrial surge standards; 33ps LOAD2 jitter ensures <±0.5LSB timing error in 16-bit systems. |
Use Scenario: Interfacing high-speed arbitrary waveform generators with isolated FPGA controllers in automated test equipment (ATE). IC Role / Device Role / Timing Role: LTM2895IY#PBF serves as isolated SPI master driving DACs while relaying status via BUSY/FAULT pins. Use Value: 100MHz SCK2 supports >50MSPS DAC update rates; 50kV/µs CMTI prevents data corruption during switching noise events. |
| Breaking Ground Loops | Medical Instrumentation |
|
Use Scenario: Eliminating measurement offset in precision sensor signal chains where analog front-end and digital processing share separate grounds. IC Role / Device Role / Timing Role: LTM2895IY#PBF isolates SPI commands to isolated ADC/DAC while passing control signals (SA2/SB2) for gain switching. Use Value: 3pF input-to-output capacitance minimizes capacitive coupling; 9.2mm creepage meets IEC 61000-4-5 surge immunity requirements. |
Use Scenario: Isolating DAC-controlled bias voltages in patient-connected ECG/EEG amplifiers requiring 2 MOPP safety compliance. IC Role / Device Role / Timing Role: LTM2895IY#PBF provides reinforced insulation (455VRMS) and 287.5VRMS 2-MOPP rating per IEC 60601-1. Use Value: CSA-certified design (File #255632) eliminates need for additional safety certification; 15mm × 6.25mm footprint saves PCB space in compact handheld devices. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar isolated SPI interface applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADUM3481CRWZ | Quad-channel digital isolator (4-channel, no integrated SPI logic or LOAD path); 25Mbps max data rate; 3750VRMS isolation | Lacks built-in SPI framing, configuration registers, and low-jitter LOAD output - requires external MCU firmware to manage SPI protocol | Select when only basic signal-level isolation is needed and full µModule integration is unnecessary |
| SI8641ED-B-IS | Quad-channel isolator with 150Mbps data rate; 5000VRMS isolation; no DAC-specific features or LOAD signal | No native SPI mode (0,0) support, no configurable SCK2, and no isolated select pass-through (SA2/SB2/SC2) | Choose for high-speed digital isolation where protocol handling is implemented externally |
Compared with ADUM3481CRWZ and SI8641ED-B-IS, the LTM2895IY#PBF uniquely integrates SPI protocol translation, configurable timing, and DAC-optimized LOAD2 synchronization in a single BGA package - reducing BOM count and layout complexity for precision analog isolation.
Availability
LTM2895IY#PBF is available at Aetrix Electronics and suitable for industrial process control, test and measurement equipment, medical instrumentation, and ground-loop elimination applications requiring stable component supply and long-term lifecycle assurance.
Supply support for LTM2895IY#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving industrial, automotive, communications, and healthcare markets.
The LTM2895IY#PBF belongs to Analog Devices' µModule isolated interface product line, engineered specifically to simplify high-fidelity analog signal chain isolation in noise-sensitive environments such as precision DAC/ADC systems and safety-critical instrumentation.
FAQ
What is the maximum SCK2 frequency supported by the LTM2895IY#PBF?
The LTM2895IY#PBF supports up to 100MHz SCK2 output frequency, configurable via its internal registers (0x30H/0x83H). At this setting, tSCK2L (SCK2 low time) is guaranteed ≥9.1ns, enabling reliable timing margins for fast DACs like the LTC2642-16. Lower frequencies (66/50/40/33/25/20/10MHz) are also selectable to match slower peripherals or reduce EMI.
Does the LTM2895IY#PBF require external configuration to operate as a basic SPI isolator?
No - the LTM2895IY#PBF operates out-of-the-box as a 4-wire SPI isolator (SS, SCK, MOSI, MISO) without configuration. Default settings support 50MHz SCK2 and 16-bit word length. Configuration registers are optional and used only to customize SCK2 frequency, word length, or enable dual-DAC mode via SSB2.
How does the LOAD→LOAD2 path function in the LTM2895IY#PBF?
The LOAD input is falling-edge sensitive and triggers a precisely timed LOAD2 pulse on the isolated side. The LTM2895IY#PBF guarantees ≤33ps RMS jitter and 12–33ns aperture delay. Pulse width depends on SCK2 frequency: ~40ns at ≥40MHz, ~60ns at ≤33MHz. Rising edges on LOAD are ignored, ensuring deterministic DAC update timing.
What safety certifications apply to the LTM2895IY#PBF?
The LTM2895IY#PBF holds CSA certification (File #255632) for UL 1577 (6000VRMS isolation), IEC 60950-1/62368-1 (reinforced insulation at 455VRMS), and IEC 60601-1 (2 MOPP at 287.5VRMS). It meets pollution degree 2, material group 3, and overvoltage category II requirements per regulatory notes.
Can the LTM2895IY#PBF interface with non-LTC DACs?
Yes - the LTM2895IY#PBF is compatible with any SPI-mode-(0,0) DAC or peripheral operating within its voltage (1.71V–5.5V VL/VL2) and timing (e.g., tDMISO ≤9.5ns) specifications. Its bidirectional isolation, configurable SCK2, and LOAD2 output make it suitable for isolating ADI, TI, Maxim, and Microchip DACs, provided they accept standard SPI framing and LDAC signals.
LTM2895IY#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 36-BGA
- Packaging:
- Tray
- Product Status:
- Active
- Technology:
- Magnetic Coupling
- Type:
- SPI
- Isolated Power:
- No
- Number of Channels:
- 9
- Inputs - Side 1/Side 2:
- 8/4
- Channel Type:
- Bidirectional, Unidirectional
- Voltage - Isolation:
- 6000Vrms
- Common Mode Transient Immunity (Min):
- 50kV/µs
- Data Rate:
- 100Mbps
- Propagation Delay tpLH / tpHL (Max):
- 150ns, 150ns
- Pulse Width Distortion (Max):
- -
- Rise / Fall Time (Typ):
- 10ns, 10ns
- Voltage - Supply:
- 3V ~ 5.5V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 36-BGA (15x6.25)
LTM2895IY#PBF FAQ
1.How can I place an order for LTM2895IY#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTM2895IY#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTM2895IY#PBF reliable?
The price and inventory of LTM2895IY#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTM2895IY#PBF is usually 5 days.
3.What payment methods are accepted for LTM2895IY#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTM2895IY#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTM2895IY#PBF?
LTM2895IY#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTM2895IY#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTM2895IY#PBF?
For technical support, including LTM2895IY#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTM2895IY#PBF requirements.
6.How does Aetrix verify that LTM2895IY#PBF is sourced from the original manufacturer or authorized distributors?
All LTM2895IY#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTM2895IY#PBF meets industry standards.
7.What is the process for return or replacement of LTM2895IY#PBF?
All LTM2895IY#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTM2895IY#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTM2895IY#PBF part is unused and in its original packaging.
Return procedure for LTM2895IY#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTM2895IY#PBF Tags
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