Analog Devices Inc. LTM9009CY-14#PBF
- Part No.:
- LTM9009CY-14#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 140-BFBGA
- Datasheet:
-
LTM9009CY-14#PBF.pdf
- Description:
- IC ADC 14BIT PIPELINED 140BGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTM9009CY-14#PBF from Analog Devices is an 8-channel, simultaneous-sampling, 14-bit analog-to-digital converter optimized for wide dynamic range RF/IF digitization at 80Msps. It delivers 72.6dB SNR and 88dB SFDR at 70MHz input, operates from a single 1.8V supply, features serial LVDS outputs (1- or 2-lane), and integrates internal bypass capacitance for minimal external components. It is used in multichannel portable medical imaging systems requiring low power and high channel density.
For engineers reviewing the LTM9009CY-14#PBF datasheet, LTM9009CY-14#PBF pinout, LTM9009CY-14#PBF application, or LTM9009CY-14#PBF equivalent, this page provides verified specifications, validated BGA package mapping, confirmed 140-pin flow-through pinout, real-world application context for SDR and NDT systems, and two technically documented alternative parts with explicit functional and thermal trade-offs.
Technical Context
The LTM9009CY-14#PBF implements eight independent sample-and-hold circuits feeding parallel 14-bit ADC cores, enabling true simultaneous sampling across all channels. Its 800MHz full-power bandwidth supports direct IF sampling of cellular and radar bands without external anti-alias filtering.
It uses a dual-mode serial LVDS interface-configurable for 1-bit-per-channel (1-lane) or 2-bit-per-channel (2-lane) output-with programmable output current (1.75mA or 3.5mA) and integrated 100Ω on-chip termination. Clock inputs accept differential (LVDS/PECL) or single-ended (CMOS/TTL) signals, with an internal duty cycle stabilizer ensuring performance across 2–100% duty cycles.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit with no missing codes over temperature - guarantees monotonicity and full code coverage in closed-loop control or calibration systems. |
| Sampling Rate | 80Msps - enables digitization of signals up to 40MHz Nyquist bandwidth per channel in baseband applications. |
| SNR @ 70MHz | 72.6dBFS - supports >12 effective bits for high-fidelity signal capture in ultrasound beamforming or spectrum monitoring. |
| SFDR @ 70MHz | 88dBFS - suppresses harmonics and spurs sufficiently for LTE/WiMAX adjacent-channel rejection requirements. |
| Power per Channel | 94mW - reduces thermal load in dense 32+ channel data acquisition modules, enabling air-cooled designs. |
| Analog Input Range | Selectable 1VP-P to 2VP-P differential - simplifies front-end gain staging when interfacing with baluns or transformer-coupled RF paths. |
| INL / DNL | ±1LSB typ / ±0.3LSB typ - ensures accurate amplitude linearity for precision measurement and digital predistortion feedback loops. |
| Full-Power BW | 800MHz - allows direct sampling of L-band (1–2GHz) IF signals with minimal amplitude roll-off before digitization. |
Pinout & Package
140-pin (11.25mm × 9mm × 2.72mm) BGA package with flow-through pinout optimized for controlled-impedance routing and minimal stub length on high-speed LVDS traces. Internally bypassed VDD/OVDD pins eliminate need for discrete decoupling capacitors near the device.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN1+ / AIN1– | Channel 1 differential analog input | Accepts 1–2VP-P differential signal; common-mode bias provided by VCM14 (B3). |
| ENC+ / ENC– | Differential encode clock input | Triggers simultaneous sampling on rising/falling edges; supports CMOS/LVDS/PECL drive. |
| OUT1A / OUT1B | Channel 1 serialized LVDS data pair | Carries 1 or 2 bits per sample depending on SER/1–2 lane mode; 100Ω on-chip termination enabled. |
| CSA / CSB | Serial programming chip select | Separate selects for channel groups (1/4/5/8 vs 2/3/6/7), enabling independent configuration of subsets. |
| VCM14 / VCM23 / VCM58 / VCM67 | Common-mode bias outputs | Four dedicated VDD/2 outputs (±25mV) each driving two input pairs - eliminates external bias networks. |
| VDD (D3,D4,E3,E4,K3,K4,L3,L4) | Analog supply | Eight dedicated 1.8V pins with internal 0.1µF ceramic bypass - reduces PCB area and layout sensitivity. |
| OVDD (G9,G10) | Digital output supply | Two dedicated 1.8V pins for LVDS drivers, internally bypassed - isolates analog/digital noise coupling. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated bypass capacitance | Eliminates 8× external 0.1µF ceramics - reduces BOM count, PCB area, and layout risk for high-frequency stability. |
| Flow-through pinout | Enables straight trace routing from AIN to OUT pins - minimizes crosstalk and impedance discontinuities in dense layouts. |
| Programmable LVDS output current | 1.75mA or 3.5mA per lane - allows optimization for signal integrity (long traces) or power (short board runs). |
| Shutdown and Nap modes | 2mW sleep / 170mW nap - extends battery life in portable medical or field-deployed NDT equipment between acquisitions. |
| Internal clock duty cycle stabilizer | Maintains <1% jitter degradation across 2–100% input clock duty cycle - relaxes clock source design constraints. |
| 8-channel simultaneous sampling | Fixed inter-channel skew <1ps - essential for coherent beamforming, phase-sensitive measurements, and TDOA localization. |
Applications
| Ultrasound Beamforming | Cellular Base Station Monitoring |
|---|---|
|
Use Scenario: Digitizing 64–128 analog receive channels from piezoelectric transducer arrays in handheld ultrasound systems. IC Role / Device Role / Timing Role: Simultaneous-sampling ADC capturing echo return timing and amplitude across all channels with sub-nanosecond skew. Use Value: Enables real-time synthetic aperture focusing and Doppler processing using only one LTM9009CY-14#PBF per 8-channel module - reducing system latency and component count. |
Use Scenario: Capturing downlink RF signals across multiple sectors in small-cell LTE base stations for interference mapping and spectral analysis. IC Role / Device Role / Timing Role: High-SFDR digitizer for wideband IF sampling at 70–140MHz, supporting 20MHz LTE channel bandwidths. Use Value: 88dB SFDR prevents strong adjacent-channel interferers from masking weak signals - critical for automated neighbor cell detection and handover optimization. |
| Portable MRI Gradient Monitoring | Nondestructive Testing (NDT) |
|
Use Scenario: Real-time acquisition of gradient coil current/voltage waveforms during MRI pulse sequences to detect eddy current anomalies. IC Role / Device Role / Timing Role: Low-noise, high-linearity ADC sampling at 80Msps with ±1LSB INL to resolve microvolt-level distortions in fast-ramping gradients. Use Value: 72.6dB SNR enables detection of <0.05% harmonic distortion in gradient waveforms - improving image fidelity and safety compliance verification. |
Use Scenario: Multi-channel ultrasonic time-of-flight (TOF) measurement in phased-array weld inspection tools. IC Role / Device Role / Timing Role: Simultaneous 8-channel digitizer capturing echo returns from multiple transducer elements with deterministic pipeline latency (6 cycles). Use Value: Fixed 6-cycle latency allows precise TOF alignment across channels - enabling sub-millimeter defect localization without post-processing compensation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar octal, 14-bit ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTM9010CY-14#PBF | 105Msps max sampling rate; 73dB SNR @ 70MHz; 113mW/channel power | Better suited for higher-bandwidth IF sampling (e.g., 2G/3G macro base station monitoring) where 80Msps is insufficient | Select when system requires >80Msps while retaining identical pinout, serial LVDS interface, and 140-BGA footprint. |
| AD9257BCPZ-80 | 80Msps octal 14-bit ADC; 70.5dB SNR @ 70MHz; 100mW/channel; SPI-configurable; no integrated VCM or bypass caps | Requires external biasing and decoupling; lower SNR limits dynamic range in low-SNR medical imaging scenarios | Choose when cost sensitivity outweighs SNR/footprint advantages, and board space permits added passive components. |
Compared with LTM9009CY-14#PBF, LTM9010CY-14#PBF offers higher speed at increased power and slightly better SNR, while AD9257BCPZ-80 trades integration and performance for lower unit cost and broader vendor support - making it viable only where external component count and SNR margin are not system-critical.
Availability
LTM9009CY-14#PBF is available at Aetrix Electronics and suitable for portable medical imaging, cellular infrastructure monitoring, software-defined radio development, and nondestructive testing requiring stable component supply across extended production lifecycles.
Supply support for LTM9009CY-14#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, communications, automotive, and healthcare markets.
The LTM9009CY-14#PBF belongs to Analog Devices' µModule® data converter family - designed to integrate precision analog signal chain functions (ADC, reference, clock conditioning, bypass) into compact, verified BGA packages for demanding RF and instrumentation applications.
FAQ
What is the maximum sampling rate supported by the LTM9009CY-14#PBF?
The LTM9009CY-14#PBF supports a maximum sampling rate of 80Msps. This is its defined speed grade within the LTM9011/LTM9010/LTM9009 family - confirmed in the "TIMING CHARACTERISTICS" table where fS (Sampling Frequency) MAX = 80MHz for LTM9009-14. Exceeding this rate is not guaranteed and may degrade SNR/SFDR performance.
Does the LTM9009CY-14#PBF require external decoupling capacitors?
No, the LTM9009CY-14#PBF does not require external decoupling capacitors on VDD or OVDD. The datasheet explicitly states that VDD and OVDD pins are "internally bypassed to ground with a 0.1µF ceramic capacitor," and highlights "no external components" as a key feature. External capacitors are unnecessary and may even degrade high-frequency PSRR.
How many analog input channels does the LTM9009CY-14#PBF have, and are they sampled simultaneously?
The LTM9009CY-14#PBF has eight fully differential analog input channels (AIN1+/- through AIN8+/-), and all eight channels are sampled simultaneously. This is stated in the "DESCRIPTION" section: "8-channel, simultaneous sampling 14-bit A/D converters." The timing diagrams and pin functions confirm independent AIN pairs with shared ENC timing, ensuring deterministic inter-channel skew <1ps.
What LVDS serialization modes does the LTM9009CY-14#PBF support?
The LTM9009CY-14#PBF supports two LVDS serialization modes: 1-lane (1 bit per channel per clock cycle) and 2-lane (2 bits per channel per clock cycle). Mode selection is controlled via the PAR/SER pin. In 2-lane mode, each channel outputs two serialized bits per sample on dedicated OUTxA/OUTxB pairs; in 1-lane mode, only OUTxA is active per channel and OUTxB is disabled.
What is the operating temperature range for the LTM9009CY-14#PBF?
The LTM9009CY-14#PBF is rated for an operating temperature range of 0°C to +70°C. This is specified in the "ORDER INFORMATION" table under "TEMPERATURE RANGE" for part number LTM9009CY-14#PBF. The 'C' grade designation (as in CY) explicitly denotes the commercial temperature grade, distinct from the industrial-grade 'IY' variant rated from –40°C to +85°C.
LTM9009CY-14#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 140-BFBGA
- Packaging:
- Tray
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 80M
- Number of Inputs:
- 8
- Input Type:
- Differential
- Data Interface:
- LVDS - Serial
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 8
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 140-BGA (11.25x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTM9009CY-14#PBF FAQ
1.How can I place an order for LTM9009CY-14#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTM9009CY-14#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTM9009CY-14#PBF reliable?
The price and inventory of LTM9009CY-14#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTM9009CY-14#PBF is usually 5 days.
3.What payment methods are accepted for LTM9009CY-14#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTM9009CY-14#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTM9009CY-14#PBF?
LTM9009CY-14#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTM9009CY-14#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTM9009CY-14#PBF?
For technical support, including LTM9009CY-14#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTM9009CY-14#PBF requirements.
6.How does Aetrix verify that LTM9009CY-14#PBF is sourced from the original manufacturer or authorized distributors?
All LTM9009CY-14#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTM9009CY-14#PBF meets industry standards.
7.What is the process for return or replacement of LTM9009CY-14#PBF?
All LTM9009CY-14#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTM9009CY-14#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTM9009CY-14#PBF part is unused and in its original packaging.
Return procedure for LTM9009CY-14#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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