Analog Devices Inc. LTM9009IY-14#PBF
- Part No.:
- LTM9009IY-14#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 140-BFBGA
- Datasheet:
-
LTM9009IY-14#PBF.pdf
- Description:
- IC ADC 14BIT PIPELINED 140BGA
- Quantity:
- Payment:

- Shipping:

Inventory:149
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Product details
Overview
LTM9009IY-14#PBF from Analog Devices is an 8-channel, simultaneous-sampling, 14-bit analog-to-digital converter with 80Msps sampling rate, 72.6dB SNR (typ), 88dB SFDR (typ), and single 1.8V supply operation. It integrates internal bypass capacitance, flow-through BGA pinout, and serial LVDS outputs for high-density multichannel data acquisition in portable medical imaging and software-defined radio front ends.
For engineers reviewing the LTM9009IY-14#PBF datasheet, LTM9009IY-14#PBF pinout, LTM9009IY-14#PBF application, or LTM9009IY-14#PBF equivalent, this page delivers verified specs including 800MHz full-power bandwidth, ±1LSB INL (typ), shutdown/nap modes, SPI configuration interface, and –40°C to +85°C industrial temperature grade - all critical for RF-sampling system design and layout optimization.
Technical Context
The LTM9009IY-14#PBF implements a parallel octal ADC architecture with independent sample-and-hold circuits per channel, enabling true simultaneous sampling across all eight inputs. Its 800MHz full-power bandwidth supports wideband IF sampling up to 140MHz input frequencies while maintaining 72.6dB SNR at –1dBFS.
Digital output uses serialized LVDS with selectable 1-lane (1-bit/channel) or 2-lane (2-bits/channel) mode, reducing I/O count versus parallel interfaces. Clock input accepts differential (LVDS/PECL) or single-ended (CMOS/TTL) signals, with internal duty cycle stabilizer ensuring consistent performance across 2–100% duty cycles at 80MHz sampling.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit with no missing codes over temperature - guarantees monotonicity and precision in measurement-critical systems. |
| Sampling Rate | 80Msps - enables digitization of wideband signals up to Nyquist frequency of 40MHz without aliasing. |
| SNR | 72.6dB (typ) at 70MHz input, –1dBFS - provides >12 effective bits for high-fidelity signal capture in SDR and medical imaging. |
| SFDR | 88dB (typ) at 70MHz input - suppresses harmonics and spurs to preserve dynamic range in crowded RF environments. |
| Power per Channel | 94mW at 80Msps, 2-lane LVDS - reduces thermal load in dense multichannel boards compared to discrete ADC solutions. |
| Analog Input Range | Selectable 1VP-P to 2VP-P differential - simplifies front-end gain staging and accommodates varying sensor or mixer output levels. |
| Full-Power Bandwidth | 800MHz - supports direct sampling of L-band and lower S-band RF signals without external track-and-hold amplifiers. |
Pinout & Package
140-pin (11.25mm × 9mm × 2.72mm) BGA package with flow-through layout optimized for signal integrity and minimal board area. Internal 0.1µF ceramic bypass capacitors eliminate need for external analog supply decoupling.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN1+ / AIN1– | Channel 1 differential analog input | Accepts 1–2VP-P differential signal; common-mode bias provided by VCM14 pin. |
| ENC+ / ENC– | Differential encode clock input | Triggers simultaneous sampling on rising/falling edges; supports 1.8V–3.3V logic families. |
| OUT1A / OUT1B | LVDS data pair for channel 1 (2-lane mode) | Serializes two bits per sample; 100Ω on-chip termination eliminates external resistors. |
| CSA / CSB | Serial chip select for channel groups | Enables independent configuration of channels 1/4/5/8 (CSA) or 2/3/6/7 (CSB) via SPI. |
| VDD / OVDD | Analog and output supply pins | Separate 1.8V supplies reduce digital noise coupling into analog core; each internally bypassed. |
| VCM14 / VCM23 / VCM58 / VCM67 | Common-mode bias outputs | Provide stable VDD/2 reference for differential input pairs; eliminate need for external bias networks. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated bypass capacitance | 0.1µF ceramic caps on VDD/OVDD pins - removes requirement for external bulk decoupling, saving PCB space and cost. |
| Flow-through BGA pinout | Input pins on one side, LVDS outputs on opposite side - minimizes trace crosstalk and simplifies routing in high-channel-count layouts. |
| Configurable serialization mode | 1-lane (1-bit/ch) or 2-lane (2-bits/ch) LVDS - balances data rate, power, and FPGA I/O resource usage based on system constraints. |
| Internal clock duty cycle stabilizer | Compensates for 2–100% input clock duty cycle - ensures consistent aperture jitter and SNR without external clock conditioning circuitry. |
| Low-latency SPI interface | 6-cycle pipeline latency with readback capability - enables real-time gain, offset, and mode adjustments during operation. |
Applications
| Software Defined Radio (SDR) | Portable Medical Ultrasound |
|---|---|
|
Use Scenario: Digitizing multiple IF or baseband channels in compact, battery-powered SDR transceivers operating across 10MHz–140MHz bands. IC Role / Device Role / Timing Role: Simultaneous-sampling octal ADC capturing quadrature I/Q streams from RF mixers with 800MHz bandwidth and 72.6dB SNR. Use Value: Enables direct-conversion architectures with no image-reject filtering overhead, reducing component count and power in handheld radios. |
Use Scenario: High-channel-count beamforming in portable ultrasound systems requiring synchronized echo digitization from 8+ transducer elements. IC Role / Device Role / Timing Role: 8-channel simultaneous ADC with <1.2LSBRMS transition noise and ±1LSB INL for precise time-of-flight measurements. Use Value: Eliminates inter-channel skew and timing mismatches that degrade image resolution, supporting real-time B-mode rendering at clinical frame rates. |
| Multichannel Data Acquisition | Nondestructive Testing (NDT) |
|
Use Scenario: High-speed monitoring of vibration, strain, or acoustic emissions across distributed sensor arrays in industrial predictive maintenance systems. IC Role / Device Role / Timing Role: Low-power (94mW/ch), 14-bit ADC with shutdown/nap modes for energy-efficient burst-mode sampling in edge nodes. Use Value: Extends battery life while preserving 88dB SFDR for detecting subtle harmonic distortions indicative of mechanical faults. |
Use Scenario: Pulse-echo ultrasonic testing of welds, composites, or pipelines using multi-element phased arrays with tight timing control. IC Role / Device Role / Timing Role: Simultaneous sampling across 8 receive channels with 0ns inter-channel delay variation and 0.15ps RMS jitter. Use Value: Ensures coherent beam synthesis and accurate defect localization without post-processing skew correction. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar octal ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD9257BCPZ-80 | 80Msps, 14-bit, 72dB SNR, but requires external reference and separate power domains for analog/digital sections. | Higher layout complexity due to external decoupling, reference, and clock conditioning; less suited for space-constrained portable designs. | Choose AD9257BCPZ-80 when system already uses ADI's reference ICs and demands tighter channel-to-channel gain matching (±0.1% vs ±0.2%). |
| ADS58J89IRGCT | 80Msps, 14-bit, 73.5dB SNR, JESD204B serial interface instead of LVDS; higher power (125mW/ch). | Requires FPGA with JESD204B IP and higher PCB layer count for high-speed differential routing; better for high-throughput backplane links. | Choose ADS58J89IRGCT when migrating to JESD204B-based systems or needing deterministic latency and multi-device synchronization. |
Compared with AD9257BCPZ-80 and ADS58J89IRGCT, the LTM9009IY-14#PBF delivers integrated power management and simplified layout via internal bypassing and flow-through pinout - reducing BOM count and validation effort in portable, multichannel instrumentation.
Availability
LTM9009IY-14#PBF is available at Aetrix Electronics and suitable for portable medical ultrasound, software-defined radio front ends, and multichannel industrial data acquisition requiring stable component supply across extended temperature ranges.
Supply support for LTM9009IY-14#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving communications, industrial, automotive, and healthcare markets.
The LTM9009IY-14#PBF belongs to the µModule® ADC family - designed to integrate precision analog signal chain components (ADC, drivers, references, power) into compact, verified BGA modules for rapid deployment in RF and instrumentation systems.
FAQ
What is the guaranteed operating temperature range for the LTM9009IY-14#PBF?
The LTM9009IY-14#PBF is rated for continuous operation from –40°C to +85°C. This industrial-grade temperature specification is confirmed in the Absolute Maximum Ratings table and applies across all key AC/DC performance parameters including SNR, SFDR, INL, and DNL - making it suitable for outdoor base stations and field-deployable medical equipment where ambient conditions vary widely.
Does the LTM9009IY-14#PBF require external bypass capacitors on its VDD and OVDD pins?
No, the LTM9009IY-14#PBF does not require external bypass capacitors on VDD or OVDD. The device integrates internal 0.1µF ceramic capacitors directly on-die for both analog and output supplies, as explicitly stated in the Pin Functions section and confirmed in the Features list. This eliminates external decoupling components and associated PCB footprint.
How many bits per channel does the LTM9009IY-14#PBF output in 2-lane LVDS mode?
In 2-lane LVDS mode, the LTM9009IY-14#PBF outputs two bits per channel per clock cycle. Each channel's 14-bit conversion result is serialized across two LVDS pairs (e.g., OUT1A/OUT1B and OUT2A/OUT2B for channel 1), with bit alignment and framing controlled by the FR+ and FR– signals - as detailed in Timing Diagram TD02 and the Digital Outputs section.
Can the LTM9009IY-14#PBF accept single-ended clock inputs?
Yes, the LTM9009IY-14#PBF supports single-ended clock inputs by tying the ENC– pin to ground and driving ENC+ with TTL, CMOS, or PECL logic. The datasheet specifies VIH = 1.2V and VIL = 0.6V for ENC+ under this configuration, and the internal duty cycle stabilizer remains active to maintain performance - enabling compatibility with standard FPGA clock outputs without differential drivers.
What is the pipeline latency of the LTM9009IY-14#PBF, and how does it affect system timing?
The LTM9009IY-14#PBF has a fixed pipeline latency of 6 clock cycles from sample initiation (ENC edge) to valid LVDS data output. This deterministic latency - specified in the Timing Characteristics table - allows precise synchronization with FPGA-based digital downconverters or beamformers, eliminating the need for variable delay calibration in time-critical applications like phased-array ultrasound or real-time spectrum analysis.
LTM9009IY-14#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 140-BFBGA
- Packaging:
- Tray
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 80M
- Number of Inputs:
- 8
- Input Type:
- Differential
- Data Interface:
- LVDS - Serial
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 8
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 140-BGA (11.25x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
LTM9009IY-14#PBF FAQ
1.How can I place an order for LTM9009IY-14#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTM9009IY-14#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTM9009IY-14#PBF reliable?
The price and inventory of LTM9009IY-14#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTM9009IY-14#PBF is usually 5 days.
3.What payment methods are accepted for LTM9009IY-14#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTM9009IY-14#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTM9009IY-14#PBF?
LTM9009IY-14#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTM9009IY-14#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTM9009IY-14#PBF?
For technical support, including LTM9009IY-14#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTM9009IY-14#PBF requirements.
6.How does Aetrix verify that LTM9009IY-14#PBF is sourced from the original manufacturer or authorized distributors?
All LTM9009IY-14#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTM9009IY-14#PBF meets industry standards.
7.What is the process for return or replacement of LTM9009IY-14#PBF?
All LTM9009IY-14#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTM9009IY-14#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTM9009IY-14#PBF part is unused and in its original packaging.
Return procedure for LTM9009IY-14#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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