Texas Instruments LV14360PDDAR

Overview

LV14360PDDAR from Texas Instruments is a 60-V, 3-A synchronous step-down DC-DC converter with integrated high-side MOSFET (155-mΩ typical), 300-µA quiescent current in sleep mode, adjustable 200 kHz–2 MHz switching frequency, and internal loop compensation. It delivers regulated power in industrial power supplies and communications equipment where wide input range (4.3 V to 60 V) and low-light-load efficiency are critical.

For engineers reviewing the LV14360PDDAR datasheet, LV14360PDDAR pinout, LV14360PDDAR application, or LV14360PDDAR equivalent, key selection considerations include its HSOIC-8 PowerPAD™ package thermal performance (RθJC(bot) = 3.8 °C/W), precision enable threshold (1.05–1.38 V), feedback reference accuracy (±1.5% over –40°C to +125°C), and soft-start capability via external capacitor on SS pin.

Technical Context

The LV14360PDDAR implements fixed-frequency peak current mode control with slope compensation to ensure stability at duty cycles >50%. Its sleep-mode operation reduces switching losses below 300 mA load, maintaining 300-µA IQ while dynamically adjusting frequency downward for high light-load efficiency.

It supports high-duty-cycle operation up to ~90% via BOOT capacitor recharge circuitry and integrates protection including cycle-by-cycle current limit (3.8–5.7 A), thermal shutdown (170°C), output overvoltage protection (±7% FB threshold), and input UVLO with 285-mV hysteresis. The RT/SYNC pin enables either resistor-programmed frequency or synchronization to an external 250 kHz–2 MHz clock with PLL lock-in time of 100 µs.

Key Specifications

Pinout & Package

LV14360PDDAR uses an 8-pin HSOIC package (4.89 mm × 3.9 mm) with exposed thermal pad (Pin 9) for low-junction-to-board resistance (RθJB = 25.5 °C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar step-down converter applications.

Compared with LM5164QPWPRQ1 and TPS54360DGQR, the LV14360PDDAR offers tighter feedback reference (±1.5% vs ±2%), lower sleep-mode IQ (300 µA vs 1.5 mA), and integrated SS functionality in an HSOIC-8 footprint - making it optimal for space-constrained industrial designs requiring simplicity and low-noise startup.

Availability

LV14360PDDAR is available at Aetrix Electronics and suitable for industrial power supplies, communications equipment, and general-purpose wide-VIN regulation requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for LV14360PDDAR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader designing analog ICs, embedded processors, and power management solutions for industrial, automotive, and communications markets.

The LV14360 product line targets high-efficiency, wide-input-voltage DC-DC conversion in space- and thermally constrained applications - emphasizing ease of use through internal compensation, programmable frequency, and integrated protection.

FAQ

What is the maximum duty cycle supported by the LV14360PDDAR?

The LV14360PDDAR supports up to approximately 90% duty cycle via its BOOT capacitor recharge circuit, enabling stable operation during low-V_IN/V_OUT dropout conditions. This is achieved by temporarily turning off the high-side MOSFET and pulling SW low to refresh BOOT when the BOOT-to-SW voltage drops below 3.2 V after five to eleven consecutive on-cycles, depending on switching frequency. The effective duty cycle is limited by MOSFET R_DS(on), inductor DCR, and diode forward voltage - all confirmed in the LV14360PDDAR datasheet Figure 7-7 (Dropout Curve).

Does the LV14360PDDAR require external compensation components?

No, the LV14360PDDAR features fully internal loop compensation, eliminating the need for external Type-II or Type-III compensation networks. This simplifies design, reduces bill-of-materials cost, and improves immunity to layout parasitics. The internal compensation is optimized for stability across the full 200 kHz–2 MHz switching frequency range and with common output capacitor types (e.g., 2 × 47 µF ceramic), as verified in Section 8.3.1 and Figure 8-2 of the LV14360PDDAR datasheet.

How is soft-start implemented on the LV14360PDDAR?

The LV14360PDDAR implements soft-start via its SS pin (Pin 6), which accepts an external capacitor (C_SS) connected to GND. An internal 3-µA current source charges C_SS, generating a linear ramp on the error amplifier's COMP node to control output voltage rise time. Soft-start duration is calculated as t_SS ≈ (0.75 V × C_SS) / 3 µA, enabling precise control of inrush current - a confirmed feature specific to the LV14360PDDAR variant, distinct from the PGOOD-capable LV14360P.

What thermal performance can be expected from the LV14360PDDAR in its HSOIC package?

The LV14360PDDAR in the HSOIC-8 PowerPAD™ package achieves RθJC(bot) = 3.8 °C/W and RθJB = 25.5 °C/W when the thermal pad is soldered to a 1-in² 2-oz copper plane. At 3 A output with 24 V input and 5 V output, typical junction-to-ambient rise is <45°C under natural convection - validated in Section 7.4 and Figure 11-2 of the LV14360PDDAR datasheet. This enables reliable operation without forced airflow in most industrial enclosures.

Can the LV14360PDDAR synchronize to an external clock, and what are the requirements?

Yes, the LV14360PDDAR supports synchronization via its RT/SYNC pin (Pin 4) to external clocks from 250 kHz to 2 MHz. Requirements include: logic-high ≥1.7 V, logic-low ≤0.5 V, minimum pulse width ≥30 ns, and falling-edge triggering. When synchronized, the internal PLL locks within 100 µs (confirmed in Section 7.6). The pin automatically reverts to resistor-programmed mode if the external clock stops - a behavior unique to the LV14360PDDAR among TI's 60-V buck family.