Texas Instruments M0G3105QDGS32RQ1
- Part No.:
- M0G3105QDGS32RQ1
- Manufacturer:
- Texas Instruments
- Category:
- Microcontrollers
- Package:
- 32-TFSOP (0.118", 3.00mm Width)
- Datasheet:
-
M0G3105QDGS32RQ1.pdf
- Description:
- AUTOMOTIVE 80MHZ ARM CORTEX-M0+
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
M0G3105QDGS32RQ1 from Texas Instruments is an automotive-grade 32-bit Arm Cortex-M0+ microcontroller with CAN-FD interface, 32KB flash, 16KB SRAM, dual 12-bit 4Msps ADCs (11-channel), and AEC-Q100 Grade 1 qualification for operation from –40°C to 125°C. It integrates GPAMP, configurable VREF, TRNG, AES-128/256, and supports body electronics, steering wheel systems, and door handle modules.
For engineers reviewing the M0G3105QDGS32RQ1 datasheet, M0G3105QDGS32RQ1 pinout, M0G3105QDGS32RQ1 application, or M0G3105QDGS32RQ1 equivalent, key selection criteria include its 32-pin VSSOP package, CAN-FD + four UARTs + two I²C + two SPI interfaces, ASIL B functional safety certification, ultra-low-power STANDBY mode (1.5µA), and automotive temperature range compliance.
Technical Context
The M0G3105QDGS32RQ1 implements a single-core Arm Cortex-M0+ CPU running at up to 80MHz with MPU, supported by SYSOSC (±1.2% accuracy), PLL, and dual crystal oscillators (HFXT/LFXT). Its analog subsystem includes two simultaneous-sampling 12-bit ADCs with hardware averaging enabling 14-bit effective resolution at 250ksps, plus one GPAMP and shared 1.4V/2.5V VREF.
Digital peripherals include a 7-channel DMA, two advanced control timers with dead-band and fault handling, five general-purpose timers (including QEI-capable and STANDBY-aware variants), two WWDTs, RTC with calendar, and full CAN-FD protocol support compliant with ISO 11898-1:2015. Power management enables RUN (101µA/MHz), SLEEP (40µA/MHz), STOP (190µA @4MHz), and STANDBY (1.5µA) modes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M0+, 80MHz max, with memory protection unit (MPU) |
| Flash / SRAM | 32KB flash with ECC, 16KB SRAM with hardware parity |
| ADC Performance | Two 12-bit 4Msps ADCs; 14-bit effective resolution at 250ksps with hardware averaging |
| Operating Range | –40°C to 125°C ambient; 1.62V–3.6V supply voltage |
| Functional Safety | ISO 26262 certified up to ASIL B; systematic capability and hardware integrity at ASIL B |
| Communication | CAN-FD (CAN 2.0 A/B compatible), 4× UART, 2× I²C (FM+, 1Mbit/s), 2× SPI (up to 32Mbit/s) |
| Low-Power Modes | STANDBY: 1.5µA (RTC + SRAM + CPU state retained); SHUTDOWN: 80nA with IO wake-up |
Pinout & Package
32-pin VSSOP package (8.1mm × 4.9mm, 0.5mm pitch), wettable flanks option available. Pin count and layout optimized for space-constrained automotive modules including door handles and kick-to-open sensors.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PA0 / FCC_IN | Functional Clock Control Input | Primary clock source for firmware-controlled clock switching; supports BSL I²C_SDA default |
| PA19 / SWDIO | Serial Wire Debug I/O | 2-pin SWD interface for programming and real-time debugging without dedicated debug header |
| PA20 / SWCLK | Serial Wire Debug Clock | Synchronizes SWD data transfer; enables in-system firmware updates and traceless debug |
| PA21 / VREF− | Analog Reference Negative | Shared negative reference for ADCs and GPAMP; configurable as GPAMP input or VREF node |
| PA22 / A0_7 | ADC0 Channel 7 Input | Single-ended or differential input for high-speed sampling; routed to ADC0 with 12-bit resolution |
| PA23 / VREF+ | Analog Reference Positive | Configurable 1.4V or 2.5V internal reference output; supplies precision bias for ADC and GPAMP |
| PA26 / A0_1 | ADC0 Channel 1 Input | General-purpose analog input with programmable gain; supports sensor signal conditioning |
| PA27 / A0_0 | ADC0 Channel 0 Input | Primary analog input channel; used for critical measurements like occupancy detection or motor current |
| NRST | Active-Low Reset | Asynchronous reset input; initiates cold boot or recovery from fault conditions |
| VDD / VSS / VCORE | Power Supply Rails | VDD (1.62–3.6V), VSS (ground), VCORE (regulated core voltage domain); decoupling required per layout guidelines |
Key Features
| Feature | Design Value |
|---|---|
| ASIL B Certification | TÜV-certified for automotive safety-critical functions; reduces system-level validation effort for body control modules |
| CAN-FD Interface | Supports data rates up to 5Mbps and payloads up to 64 bytes; enables high-bandwidth gateway communication in vehicle networks |
| Dual Simultaneous ADCs | Two independent 12-bit 4Msps converters allow synchronized sampling of motor phase currents and temperature sensors |
| Ultra-Low-Power STANDBY | 1.5µA retention mode preserves RTC, SRAM, and CPU context-ideal for occupancy detection with instant wake-on-IO |
| Hardware Security | AES-128/256 encryption engine and TRNG enable secure firmware updates and cryptographic key generation in resource-constrained nodes |
| GPAMP + Configurable VREF | Integrated general-purpose amplifier with selectable gain and dual-reference (1.4V/2.5V) simplifies analog front-end design for Hall-effect or thermistor signals |
Applications
| Automotive Door Handle Module | Steering Wheel Control System |
|---|---|
Use Scenario: Proximity sensing and mechanical actuation in keyless entry systems with capacitive touch and hall-effect feedback. IC Role / Device Role / Timing Role: Real-time sensor fusion hub managing ADC inputs, CAN-FD command dispatch, and low-latency GPIO-driven solenoid control. Use Value: 11-channel ADC support enables multi-sensor integration; STANDBY mode (1.5µA) extends battery life in passive entry applications. |
Use Scenario: Multi-function button and rotary encoder processing with haptic feedback and CAN message routing. IC Role / Device Role / Timing Role: Central MCU executing UI logic, QEI-based position tracking, and CAN-FD gateway between LIN and vehicle backbone. Use Value: QEI-capable timer (TIMG12) delivers precise rotary input capture; four UARTs support concurrent LIN diagnostics and debug logging. |
| Kick-to-Open Rear Trunk System | Vehicle Occupancy Detection Node |
Use Scenario: Foot-motion detection using capacitive or ultrasonic sensors, coupled with secure authentication and latch actuation. IC Role / Device Role / Timing Role: Sensor preprocessing unit with GPAMP signal conditioning, AES-encrypted CAN-FD reporting, and wake-on-IO from motion triggers. Use Value: Integrated GPAMP and VREF eliminate external op-amp components; SHUTDOWN mode (80nA) enables years-long battery operation. |
Use Scenario: Seat-mounted pressure and thermal sensing for occupant classification and airbag deployment logic. IC Role / Device Role / Timing Role: Analog acquisition node performing simultaneous sampling of multiple seat sensors and transmitting fused data via CAN-FD. Use Value: Dual simultaneous ADCs ensure time-aligned pressure/temperature readings; ASIL B certification satisfies airbag system functional safety requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M0G3105QRHBRQ1 | Same core, memory, and peripheral set; 32-pin VQFN (5mm × 5mm) instead of VSSOP | Better thermal performance and higher board-level reliability in vibration-prone environments | Select for mechanically demanding locations (e.g., suspension-mounted ECUs) where VQFN's solder joint robustness is preferred |
| M0G3106QDGS32RQ1 | 64KB flash / 32KB SRAM; identical package, pinout, and peripheral configuration | Enables larger firmware images with OTA update capability and expanded diagnostic logging buffers | Select when future-proofing for feature-rich software stacks or extended diagnostic coverage without PCB redesign |
Compared with M0G3105QDGS32RQ1, the VQFN alternative improves mechanical reliability under shock/vibration, while the 64KB flash variant provides headroom for complex safety monitors and secure boot extensions-both retain identical CAN-FD timing, ADC performance, and ASIL B certification scope.
Availability
M0G3105QDGS32RQ1 is available at Aetrix Electronics and suitable for automotive body electronics, steering wheel systems, and door handle modules requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for M0G3105QDGS32RQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog and embedded processing solutions for automotive, industrial, and personal electronics markets.
The M0G3105QDGS32RQ1 belongs to the MSPM0G310x-Q1 family-ultra-low-power, AEC-Q100 qualified MCUs designed specifically for cost-sensitive automotive body control, lighting, and comfort applications with integrated analog and functional safety features.
FAQ
What is the maximum operating frequency of the M0G3105QDGS32RQ1?
The M0G3105QDGS32RQ1 features an Arm Cortex-M0+ CPU with a maximum operating frequency of 80MHz, achieved via internal PLL or direct HFXT input. This frequency is fully supported across the full –40°C to 125°C temperature range and 1.62V–3.6V supply voltage window, with timing validated per TI's SLASF86C specification.
Does the M0G3105QDGS32RQ1 support CAN-FD with ISO 11898-1:2015 compliance?
Yes, the M0G3105QDGS32RQ1 integrates a CAN-FD controller compliant with ISO 11898-1:2015, supporting both classical CAN 2.0 A/B and FD frames with bit rates up to 5Mbps and payloads up to 64 bytes. Physical layer compliance requires external transceiver; the MCU handles protocol stack, filtering, and RAM-based message buffering.
How many analog input channels does the M0G3105QDGS32RQ1 support in its 32-pin VSSOP package?
In the 32-pin VSSOP (DGS32) package, the M0G3105QDGS32RQ1 supports 11 external analog input channels-allocated across ADC0 and ADC1. This is confirmed in Table 5-1 of the SLASF86C datasheet, which specifies "2 / 11" for ADC/CHAN in the M0G3105QDGS32RQ1 row.
Is the M0G3105QDGS32RQ1 qualified for automotive use under AEC-Q100?
Yes, the M0G3105QDGS32RQ1 is AEC-Q100 Grade 1 qualified, rated for operation from –40°C to 125°C ambient temperature. It also carries ISO 26262 ASIL B certification (TÜV assessed), covering both systematic capability and hardware integrity for functional safety applications in automotive body electronics.
What debug interface does the M0G3105QDGS32RQ1 provide, and how many pins does it require?
The M0G3105QDGS32RQ1 provides a 2-pin Serial Wire Debug (SWD) interface using PA19 (SWDIO) and PA20 (SWCLK). This minimal footprint enables in-circuit programming and real-time debugging without requiring additional debug headers or JTAG pins, preserving I/O for application signals in the compact 32-pin VSSOP layout.
M0G3105QDGS32RQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 32-TFSOP (0.118", 3.00mm Width)
- Series:
- MSPM0 G
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M0+
- Core Size:
- 32-Bit
- Speed:
- 80MHz
- Connectivity:
- CANbus, DALI, I2C, IrDA, LINbus, SmartCard, SMBus, SPI, UART/USART
- Peripherals:
- AES, Brown-out Detect/Reset, DMA, POR, PWM, TRNG, WDT
- Number of I/O:
- 28
- Program Memory Size:
- 32KB (32K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 16K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.62V ~ 3.6V
- Data Converters:
- A/D 11x12b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
M0G3105QDGS32RQ1 FAQ
1.How can I place an order for M0G3105QDGS32RQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for M0G3105QDGS32RQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M0G3105QDGS32RQ1 reliable?
The price and inventory of M0G3105QDGS32RQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M0G3105QDGS32RQ1 is usually 5 days.
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5.How can I obtain technical support or documentation for M0G3105QDGS32RQ1?
For technical support, including M0G3105QDGS32RQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M0G3105QDGS32RQ1 requirements.
6.How does Aetrix verify that M0G3105QDGS32RQ1 is sourced from the original manufacturer or authorized distributors?
All M0G3105QDGS32RQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M0G3105QDGS32RQ1 meets industry standards.
7.What is the process for return or replacement of M0G3105QDGS32RQ1?
All M0G3105QDGS32RQ1 units undergo pre-shipment inspection (PSI). If there is an issue with M0G3105QDGS32RQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M0G3105QDGS32RQ1 part is unused and in its original packaging.
Return procedure for M0G3105QDGS32RQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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