STMicroelectronics M24128-DFCS6TP/K
- Part No.:
- M24128-DFCS6TP/K
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-UFBGA, WLCSP
- Datasheet:
-
M24128-DFCS6TP/K.pdf
- Description:
- IC EEPROM 128KBIT I2C 8WLCSP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
M24128-DFCS6TP/K from STMicroelectronics is a 128-Kbit I²C-compatible EEPROM organized as 16 K × 8 bits, featuring hardware write protection via WC pin, 64-byte identification page, and operation from 1.7 V to 5.5 V across –40 °C to +85 °C. It supports Fast-mode Plus (1 MHz), Fast-mode (400 kHz), and Standard-mode (100 kHz) I²C bus timing, and is used in industrial sensor calibration storage, embedded system configuration retention, and secure parameter backup.
For engineers reviewing the M24128-DFCS6TP/K datasheet, M24128-DFCS6TP/K pinout, M24128-DFCS6TP/K application, or M24128-DFCS6TP/K equivalent, key selection considerations include its 1.7–5.5 V supply range, WC-controlled hardware write lock, 64-byte ID page with permanent read-only lock capability, and WLCSP8 package footprint for space-constrained PCBs.
Technical Context
The device implements an I²C target interface with open-drain SDA and input SCL, supporting standard, fast, and fast-plus modes. Chip enable is controlled by E2/E1/E0 pins (hardwired to 000 in WLCSP8), and write control (WC) disables all writes when high - including byte, page, and ID page operations.
Memory organization includes two distinct address spaces: main array (16 Kbytes, 64-byte pages) and dedicated 64-byte identification page. ECC logic (enabled in process letter K devices) corrects single-bit errors per 4-byte group, and internal address counter auto-increments during sequential reads with rollover at boundary.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 128 Kbit (16 K × 8), enabling storage of firmware config, calibration data, or device IDs in compact systems |
| I²C speed support | Up to 1 MHz (Fast-mode Plus), allowing high-throughput parameter updates without bus contention |
| Supply voltage range | 1.7 V to 5.5 V (–40 °C to +85 °C), compatible with Li-ion, 3.3 V, and 5 V logic domains |
| Write endurance | 4 million cycles, supporting frequent recalibration or logging in field-deployed equipment |
| Data retention | 200 years at +85 °C, ensuring long-term reliability in automotive or industrial control modules |
| Page size | 64 bytes, optimizing burst writes while minimizing bus occupancy and power consumption |
| ID page | 64-byte dedicated area with permanent lock capability, used for storing immutable serial numbers or security keys |
Pinout & Package
Package: WLCSP8 (1.289 × 1.099 mm), ultra-compact wafer-level chip-scale package suitable for wearables, medical sensors, and miniaturized IoT nodes.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VSS | Ground reference | Return path for all internal circuitry; must be low-impedance and decoupled near package |
| WC | Write control input | Active-high hardware lock: disables all write operations (byte/page/ID) when driven high |
| E0 | Chip enable LSB | Hardwired low in WLCSP8; sets device address bit b1 = 0 for I²C select code (1010xxx0) |
| E1 | Chip enable middle bit | Hardwired low in WLCSP8; sets device address bit b2 = 0 for I²C select code (1010xxx0) |
| E2 | Chip enable MSB | Hardwired low in WLCSP8; sets device address bit b3 = 0 for I²C select code (1010xxx0) |
| VCC | Supply voltage | 1.7–5.5 V input; requires local 10–100 nF decoupling capacitor for stable internal charge pump operation |
| SCL | Serial clock input | Master-generated clock; rising edge samples SDA, falling edge allows SDA transition |
| SDA | Serial data I/O | Open-drain bidirectional line; requires external pull-up resistor (value depends on bus capacitance and speed) |
Key Features
| Feature | Design Value |
|---|---|
| Hardware write protection | WC pin disables all write operations - including ID page programming - preventing accidental corruption during power transitions |
| Dedicated identification page | 64-byte memory region with permanent lock command, enabling secure storage of unique identifiers or cryptographic keys |
| ECC error correction | Single-bit correction per 4-byte group (process letter K), improving read reliability in noisy or aging environments |
| Multi-voltage operation | 1.7 V minimum supply enables direct interfacing with ultra-low-power MCUs (e.g., STM32L4/L5) without level shifters |
| Fast-mode Plus support | 1 MHz I²C clock tolerance reduces configuration time by up to 2.5× vs. Standard-mode, critical for production-line programming |
Applications
| Industrial Sensor Calibration | Medical Device Configuration |
|---|---|
|
Use Scenario: Storing factory-calibrated offset/gain coefficients for pressure, temperature, and humidity sensors in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile parameter store accessed during boot and runtime via I²C; WC pin held high after calibration to prevent field overwrite. Use Value: Eliminates need for external OTP or flash, reducing BOM count and enabling field recalibration without firmware update. |
Use Scenario: Retaining user-adjusted therapy parameters (e.g., infusion rate, alarm thresholds) across power cycles in portable insulin pumps. IC Role / Device Role / Timing Role: Secure configuration EEPROM with ID page locked to store device serial number and regulatory compliance flags. Use Value: Meets IEC 62304 traceability requirements via immutable ID page, while supporting >4M write cycles for frequent parameter changes. |
| Automotive Body Control Module | Smart Meter Firmware Backup |
|
Use Scenario: Saving seat/mirror position memory and lighting presets in 12 V vehicle architectures with wide supply transients. IC Role / Device Role / Timing Role: Voltage-tolerant EEPROM interfaced directly to 3.3 V MCU I²C bus; operates down to 1.7 V during cold-crank events. Use Value: Maintains settings through battery voltage dips below 6 V, avoiding reinitialization after engine start. |
Use Scenario: Backing up meter firmware checksums and tariff tables during firmware OTA updates in AMI smart meters. IC Role / Device Role / Timing Role: High-reliability storage with 200-year data retention, accessed only during verified update sequences using WC-controlled write gating. Use Value: Prevents bricking during power loss mid-update by enabling atomic write validation and rollback via ID page integrity check. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT24C128C-SSHL-T | No identification page; no WC pin; only software write protection; 1.7–5.5 V, 1 MHz I²C | Lacks hardware lock and ID page - unsuitable for secure serial number storage or fail-safe calibration retention | Select when cost sensitivity outweighs need for permanent ID locking or robust hardware write disable |
| BR24G128FJ-WE2 | 1.6–5.5 V; built-in write protect register (WP); no dedicated ID page; 1 MHz I²C; 1 million write cycles | Software-configurable WP register offers flexible zone protection but lacks permanent lock capability of ID page | Prefer for designs requiring dynamic write-enable control across memory regions, not fixed immutable storage |
Compared with AT24C128C-SSHL-T and BR24G128FJ-WE2, the M24128-DFCS6TP/K uniquely combines hardware WC-based write disable, permanent ID page lock, and ECC-enhanced reliability - making it optimal for safety-critical or tamper-resistant applications where parameter immutability is mandated.
Availability
M24128-DFCS6TP/K is available at Aetrix Electronics and suitable for industrial sensor calibration, medical device configuration, and automotive body control modules requiring stable component supply with guaranteed long-term availability.
Supply support for M24128-DFCS6TP/K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and memory solutions for industrial, automotive, and consumer markets.
The M24128 series belongs to ST's serial EEPROM product line, engineered specifically for robust, low-voltage, high-endurance nonvolatile storage in space-constrained and mission-critical embedded systems.
FAQ
What is the function of the WC pin on the M24128-DFCS6TP/K?
The WC (Write Control) pin is an active-high hardware lock that disables all write operations - including byte, page, and identification page writes - when driven high. It remains effective regardless of I²C command sequence or address, providing fail-safe protection against unintended overwrites during power-up, noise events, or firmware bugs. Pulling WC low or leaving it floating enables normal write functionality.
Does the M24128-DFCS6TP/K support permanent locking of the identification page?
Yes - the M24128-DFCS6TP/K supports a dedicated "lock identification page" instruction that permanently disables all future writes to the 64-byte ID page. Once locked, the page becomes read-only for the lifetime of the device. This is implemented via an irreversible fuse-like mechanism in the silicon, confirmed by NO ACK response to subsequent write attempts to the ID page.
How does ECC operate in the M24128-DFCS6TP/K, and which process variants include it?
ECC (Error Correction Code) is embedded only in devices marked with process letter K (as indicated in the full part number suffix). It performs single-bit correction per 4-byte group transparently during read operations. During writes, ECC logic automatically updates all four bytes in the affected group, distributing endurance wear across the group - meaning total cycles are budgeted per group, not per byte.
Can the M24128-DFCS6TP/K be used with a 1.6 V supply?
No - the M24128-DFCS6TP/K is rated for 1.7 V minimum supply across its full operating temperature range (–40 °C to +85 °C). While some M24128-DF variants may support 1.6 V under restricted conditions (e.g., limited temperature range or reduced speed), this specific WLCSP8 variant (DFCS6TP/K) does not meet specification below 1.7 V and must not be operated below that threshold.
M24128-DFCS6TP/K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-UFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 450 ns
- Voltage - Supply:
- 1.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WLCSP
M24128-DFCS6TP/K FAQ
1.How can I place an order for M24128-DFCS6TP/K through Aetrix?
Please submit a Request for Quotation (RFQ) for M24128-DFCS6TP/K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M24128-DFCS6TP/K reliable?
The price and inventory of M24128-DFCS6TP/K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M24128-DFCS6TP/K is usually 5 days.
3.What payment methods are accepted for M24128-DFCS6TP/K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M24128-DFCS6TP/K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M24128-DFCS6TP/K?
M24128-DFCS6TP/K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M24128-DFCS6TP/K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M24128-DFCS6TP/K?
For technical support, including M24128-DFCS6TP/K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M24128-DFCS6TP/K requirements.
6.How does Aetrix verify that M24128-DFCS6TP/K is sourced from the original manufacturer or authorized distributors?
All M24128-DFCS6TP/K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M24128-DFCS6TP/K meets industry standards.
7.What is the process for return or replacement of M24128-DFCS6TP/K?
All M24128-DFCS6TP/K units undergo pre-shipment inspection (PSI). If there is an issue with M24128-DFCS6TP/K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M24128-DFCS6TP/K part is unused and in its original packaging.
Return procedure for M24128-DFCS6TP/K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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