STMicroelectronics M24C04-DRMN3TP/K
- Part No.:
- M24C04-DRMN3TP/K
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
M24C04-DRMN3TP/K.pdf
- Description:
- IC EEPROM 4KBIT I2C 1MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,245
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
M24C04-DRMN3TP/K from STMicroelectronics is an AEC-Q100 Grade 1 automotive serial EEPROM with 4 Kbits (512 × 8) memory, I²C interface supporting up to 1 MHz, 16-byte page size, and extended operation from −40 °C to 125 °C at 1.7 V–5.5 V. It integrates ECC for single-bit error correction and includes a write-lockable 16-byte identification page used for device ID storage and application parameter retention in vehicle control modules.
For engineers reviewing the M24C04-DRMN3TP/K datasheet, M24C04-DRMN3TP/K pinout, M24C04-DRMN3TP/K application, or M24C04-DRMN3TP/K equivalent, key selection criteria include automotive temperature compliance, I²C clock speed support (1 MHz), byte/page write timing (≤4 ms), write endurance at 125 °C (600 k cycles), and identification page lockability for secure parameter storage.
Technical Context
The M24C04-DRMN3TP/K implements a true EEPROM array organized into 32 pages of 16 bytes each, with embedded ECC logic correcting single-bit errors during read operations. Its I²C interface complies fully with standard, fast, and high-speed modes (100 kHz/400 kHz/1 MHz), using open-drain SDA with external pull-up and Schmitt-triggered SCL/E1/E2/WC inputs for robust noise immunity.
Chip enable (E1, E2) pins configure the 2-bit address portion of the 7-bit I²C device select code (1010b for memory, 1011b for ID page), enabling up to four devices on one bus. The WC pin provides hardware-level write protection: high = full memory write inhibit; low or floating = write enabled - including to the 16-byte identification page, which supports permanent lock via dedicated instruction.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 4 Kbits (512 bytes), organized as 32 × 16-byte pages - enables efficient firmware parameter storage with page-aligned writes. |
| I²C clock frequency | Up to 1 MHz - supports high-throughput configuration updates in real-time automotive subsystems like body control modules. |
| Write cycle time | ≤4 ms for byte or page write - minimizes bus occupancy and enables deterministic timing in safety-critical boot sequences. |
| Endurance @ 125 °C | 600 k write cycles - ensures reliable calibration data logging over full vehicle lifetime under hood-high-temp conditions. |
| Data retention @ 125 °C | 50 years - guarantees persistent storage of VIN, calibration IDs, and security keys without refresh in engine control units. |
| Supply voltage range | 1.7 V to 5.5 V - interoperates across 3.3 V and 5 V automotive domains without level-shifting circuitry. |
| ESD protection | 4000 V HBM - withstands handling and board assembly stresses in Tier-1 manufacturing environments. |
Pinout & Package
Package: SO8N (MN), 150 mil width, RoHS-compliant and halogen-free (ECOPACK2®).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1: SDA | Serial Data I/O | Open-drain bidirectional bus line - requires external pull-up; supports wire-OR with other I²C devices. |
| 2: VSS | Ground | Reference return path for VCC and all logic signals - must be low-impedance for stable ECC and write timing. |
| 3: SCL | Serial Clock Input | Schmitt-triggered clock input - rejects noise spikes and ensures clean edge sampling up to 1 MHz. |
| 4: WC | Write Control | Hardware write lock: high = full memory write disabled; low/floating = write enabled - critical for preventing corruption during power transients. |
| 5: E1 | Chip Enable Bit 1 | Configures bit b2 of I²C device address (1010b/1011b) - tied high/low to assign unique bus address among up to four devices. |
| 6: NC | No Connect | Internally unused pin - must remain unconnected per datasheet; no routing or grounding allowed. |
| 7: VCC | Supply Voltage | Power input (1.7–5.5 V) - requires local 10–100 nF decoupling capacitor to maintain voltage stability during internal write cycles. |
| 8: E2 | Chip Enable Bit 2 | Configures bit b3 of I²C device address - used with E1 to select one of four possible addresses on shared I²C bus. |
Key Features
| Feature | Design Value |
|---|---|
| AEC-Q100 Grade 1 qualification | Validated for −40 °C to 125 °C operation with full reliability testing - meets functional safety requirements for ASIL-B systems. |
| Embedded ECC (x1) | Corrects single-bit errors on every read - eliminates need for software CRC checks and improves data integrity in noisy ECU environments. |
| Dedicated 16-byte ID page | Factory-programmed ST device ID + user-writable space - enables secure traceability and immutable storage of calibration constants or cryptographic keys. |
| Hardware write lock (WC pin) | Prevents accidental writes during brown-out, reset, or firmware update - avoids memory corruption without software intervention. |
| 1 MHz I²C interface | Reduces configuration time by 4× vs. 250 kHz parts - accelerates boot-time parameter loading in ADAS domain controllers. |
Applications
| Engine Control Unit (ECU) | Body Control Module (BCM) |
|---|---|
|
Use Scenario: Storing and updating engine calibration maps, fault codes, and mileage counters across vehicle lifetime. IC Role / Device Role / Timing Role: Nonvolatile parameter storage with ECC-protected reads and hardware write lock during ignition cycling. Use Value: Ensures 50-year data retention at 125 °C under hood, eliminating periodic refresh and reducing ECU BOM cost vs. FRAM. |
Use Scenario: Retaining door lock settings, lighting profiles, and seat position memory after battery disconnect. IC Role / Device Role / Timing Role: Low-voltage (1.7 V) I²C EEPROM interfacing directly with 3.3 V microcontroller GPIOs. Use Value: Operates down to 1.7 V during cold-crank events, preventing loss of user preferences when battery dips below 2.0 V. |
| Advanced Driver Assistance Systems (ADAS) | Electric Power Steering (EPS) |
|
Use Scenario: Securely storing camera alignment offsets and radar fusion parameters updated during dealer calibration. IC Role / Device Role / Timing Role: Identification page locked after programming to prevent tampering with safety-critical sensor metadata. Use Value: Provides cryptographically verifiable origin of calibration data via factory-written ID bytes (20h/E0h/09h). |
Use Scenario: Logging torque sensor zero-point drift compensation values across motor thermal cycles. IC Role / Device Role / Timing Role: High-endurance (600 k cycles @ 125 °C) EEPROM co-located with EPS MCU for real-time wear compensation. Use Value: Survives >10 years of repeated thermal stress without degradation - outperforms standard EEPROMs rated only to 85 °C. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT24C04C-SSHM-T (Microchip) | Same 4-Kbit capacity, AEC-Q100 Grade 2 (−40 °C to 105 °C), no identification page or ECC. | Lacks ID page lock and ECC - unsuitable for ASIL-B systems requiring fault-tolerant reads. | Select only for non-safety-critical cabin modules where 105 °C max temp suffices. |
| BR24G04NUX-3GE2 (ROHM) | AEC-Q100 Grade 1, 1 MHz I²C, but no dedicated ID page; uses software write-protect instead of WC pin. | Requires firmware coordination for write protection - increases risk of corruption during interrupt latency or reset. | Prefer when pin count is constrained and hardware lock is not required for system architecture. |
Compared with AT24C04C-SSHM-T and BR24G04NUX-3GE2, the M24C04-DRMN3TP/K uniquely combines Grade 1 temperature rating, hardware WC pin lock, factory-programmed ID page, and ECC - making it the only choice for ASIL-B-compliant storage of calibration and security data in powertrain and ADAS ECUs.
Availability
M24C04-DRMN3TP/K is available at Aetrix Electronics and suitable for engine control units, body control modules, ADAS domain controllers, and electric power steering systems requiring stable component supply across automotive production lifecycles.
Supply support for M24C04-DRMN3TP/K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader specializing in automotive, industrial, and power management ICs, with broad portfolio certification to AEC-Q100 and ISO 26262 standards.
The M24C04-DRMN3TP/K belongs to ST's automotive-grade serial EEPROM product line, designed specifically for reliable, long-term nonvolatile storage in harsh-temperature vehicle subsystems where data integrity and security are mission-critical.
FAQ
What is the function of the WC pin on the M24C04-DRMN3TP/K?
The WC (Write Control) pin is a hardware-level write protection input. When driven high, it disables all write operations to both the main memory array and the identification page - preventing accidental or malicious modification during power transients, resets, or firmware updates. When low or left floating, writes are enabled. This behavior is implemented entirely in silicon and requires no software overhead.
How does the identification page differ from the main memory array?
The identification page is a separate 16-byte region accessible via I²C device type identifier 1011b (vs. 1010b for main memory). It contains three factory-programmed bytes (ST manufacturer code 20h, I²C family code E0h, density code 09h) followed by 13 user-writable bytes. Once locked via the dedicated "lock ID" instruction, the entire page becomes permanently read-only - unlike main memory, which supports standard byte/page writes without lock capability.
Does the M24C04-DRMN3TP/K support standard I²C addressing with multiple devices on one bus?
Yes - the E1 and E2 pins configure bits b2 and b3 of the 7-bit I²C device address, allowing up to four M24C04-DRMN3TP/K devices to share a single I²C bus. Each device responds only when its E1/E2 combination matches the corresponding bits in the transmitted device select code (1010b for memory, 1011b for ID page), enabling scalable parameter storage across distributed automotive ECUs without address conflicts.
What is the role of ECC in this EEPROM, and how is it implemented?
The M24C04-DRMN3TP/K includes embedded single-bit error correction code (ECC x1) logic applied transparently to every 8-bit memory word. During read operations, if one bit flips due to radiation or aging, ECC detects and corrects it in real time - returning valid data without CPU intervention. This eliminates the need for external CRC validation or redundant storage, improving system reliability in safety-critical automotive applications without increasing firmware complexity.
M24C04-DRMN3TP/K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 512 x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 4ms
- Access Time:
- 450 ns
- Voltage - Supply:
- 1.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
M24C04-DRMN3TP/K FAQ
1.How can I place an order for M24C04-DRMN3TP/K through Aetrix?
Please submit a Request for Quotation (RFQ) for M24C04-DRMN3TP/K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M24C04-DRMN3TP/K reliable?
The price and inventory of M24C04-DRMN3TP/K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M24C04-DRMN3TP/K is usually 5 days.
3.What payment methods are accepted for M24C04-DRMN3TP/K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M24C04-DRMN3TP/K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M24C04-DRMN3TP/K?
M24C04-DRMN3TP/K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M24C04-DRMN3TP/K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M24C04-DRMN3TP/K?
For technical support, including M24C04-DRMN3TP/K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M24C04-DRMN3TP/K requirements.
6.How does Aetrix verify that M24C04-DRMN3TP/K is sourced from the original manufacturer or authorized distributors?
All M24C04-DRMN3TP/K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M24C04-DRMN3TP/K meets industry standards.
7.What is the process for return or replacement of M24C04-DRMN3TP/K?
All M24C04-DRMN3TP/K units undergo pre-shipment inspection (PSI). If there is an issue with M24C04-DRMN3TP/K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M24C04-DRMN3TP/K part is unused and in its original packaging.
Return procedure for M24C04-DRMN3TP/K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
M24C04-DRMN3TP/K Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
