Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Memory > Memory

STMicroelectronics M24C04-RMN6TP

Name: M24C04-RMN6TP
Brand: STMicroelectronics
SKU: M24C04-RMN6TP
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: M24C04-RMN6TP

Manufacturer:: STMicroelectronics

Category:: Memory

Package:: 8-SOIC (0.154", 3.90mm Width)

Datasheet:: M24C04-RMN6TP.pdf

Description:: IC EEPROM 4KBIT I2C 400KHZ 8SOIC

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:9,574

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

M24C04-RMN6TP from STMicroelectronics is a 4-Kbit I²C-compatible serial EEPROM organized as 512 × 8 bits, operating at up to 400 kHz clock frequency with 1.8 V to 5.5 V single-supply voltage. It features 16-byte page write capability, 4 million write cycles endurance, and 200-year data retention at 55 °C - deployed in industrial sensor calibration storage and embedded system configuration memory.

For engineers reviewing the M24C04-RMN6TP datasheet, M24C04-RMN6TP pinout, M24C04-RMN6TP application, or M24C04-RMN6TP equivalent, key selection considerations include supply voltage compatibility (1.8–5.5 V), I²C bus timing compliance (400 kHz max), write-protect control via WC pin, and package-specific pin mapping for TSSOP8 (MN) footprint.

Technical Context

The M24C04-RMN6TP implements a standard I²C slave protocol with start/stop detection, ACK/NACK handshaking, and 7-bit device addressing where E1/E2 pins configure the two MSB address bits (b3,b2). Its internal architecture includes a page latch, X/Y decoders, HV generator for EEPROM programming, and automatic address incrementing during sequential read.

Write protection is hardware-enforced via the WC input: high level disables all writes to the full 512-byte array, while low or floating enables byte/page writes. The device integrates power-on reset (POR) to prevent spurious writes during power ramp-up, and supports both random and sequential read modes with roll-over addressing (except in DFN5 package).

Key Specifications

Parameter	Value and Actual Design Meaning
Memory size	4 Kbit (512 × 8 bits) - sufficient for firmware revision flags, sensor offset tables, or secure boot keys in compact embedded systems.
I²C clock frequency	Up to 400 kHz - compatible with standard/fast-mode I²C controllers without requiring clock stretching support.
Supply voltage range	1.8 V to 5.5 V - supports direct interfacing with 1.8 V logic (e.g., microcontrollers with low-V_CC IO) and legacy 5 V systems.
Write cycle endurance	4 million cycles at 25 °C - enables daily reconfiguration over >10 years in field-deployed telemetry nodes.
Data retention	200 years at 55 °C - guarantees long-term integrity of calibration data in unattended industrial monitoring equipment.
Page size	16 bytes - optimizes write efficiency for parameter blocks aligned to common MCU register widths (e.g., 4×32-bit config sets).
Operating temperature	−40 °C to +85 °C - qualified for use in automotive body control modules and outdoor environmental sensors.

Pinout & Package

Package: TSSOP8 (ECOPACK2), 169 mil width, RoHS-compliant and halogen-free. Pin 1 identified by notch or dot marking; pin numbering counterclockwise from top-left corner when marking side faces up.

Pin/Terminal	Circuit Role	Design Meaning
1 - E2	Chip enable (address bit b2)	Hardwired to VSS or VCC to set device I²C address; floating reads as low (0); not connected in DFN5 variant.
2 - E1	Chip enable (address bit b3)	Configures second address bit; must be stable before I²C start condition; unused in DFN5 package.
3 - SDA	Serial data I/O	Open-drain bidirectional line requiring external pull-up; shares bus with other I²C slaves; supports wired-AND arbitration.
4 - VSS	Ground reference	Primary return path for all signals and VCC decoupling; must be low-impedance connection to minimize noise coupling.
5 - SCL	Serial clock input	Master-generated clock strobe; rising edge samples SDA input, falling edge drives SDA output; must meet t_RISE/t_FALL ≤ 50 ns.
6 - WC	Write control input	Active-high hardware write protect: high = all writes inhibited; low or floating = writes enabled; no software lock required.
7 - VCC	Supply voltage	1.8–5.5 V DC input; requires local 10–100 nF ceramic decoupling capacitor between VCC and VSS near package pins.
8 - E1 (NC)	No connect (TSSOP8 only)	Not internally bonded in TSSOP8; left unconnected per ECOPACK2 design - no routing or termination needed.

Key Features

Feature	Design Value
Hardware write protection	WC pin disables entire memory array from writes - eliminates risk of accidental corruption during firmware updates or brown-out events.
Extended voltage operation	1.8 V minimum supply enables direct interface with ultra-low-power MCUs (e.g., STM32L0/L4) without level shifters.
High endurance & retention	4M write cycles and 200-year data retention validated per JEDEC JESD22-A117 - suitable for lifetime-critical calibration storage.
I²C fast-mode support	400 kHz clock tolerance with guaranteed t_LOW/t_HIGH and setup/hold timing - interoperable with most ARM Cortex-M and RISC-V I²C peripherals.
Enhanced robustness	3 kV HBM ESD rating and latch-up immunity per JESD78 - withstands handling and board-level ESD events in manufacturing environments.

Applications

Industrial Sensor Calibration

Embedded System Configuration

Use Scenario: Storing factory-calibrated temperature/pressure offset coefficients in smart transmitters deployed in oil & gas pipelines.

IC Role / Device Role / Timing Role: Nonvolatile configuration storage accessed at power-up via I²C; retains values across 15+ year service life without battery backup.

Use Value: Eliminates need for external battery-backed SRAM; enables recalibration in-field using same I²C interface used for sensor data reads.

Use Scenario: Holding boot-time parameters (UART baud rate, display brightness, network MAC address) in medical infusion pumps.

IC Role / Device Role / Timing Role: I²C slave providing persistent settings storage; accessed during initialization sequence before real-time OS starts.

Use Value: Ensures consistent user-configured behavior across power cycles and firmware updates without host MCU flash wear.

Automotive Body Control

IoT Edge Node Identity

Use Scenario: Recording door lock actuation counts and mirror position presets in vehicle body control units (BCUs).

IC Role / Device Role / Timing Role: Low-voltage EEPROM interfaced to 3.3 V CAN microcontroller; operates reliably at −40 °C cold cranking conditions.

Use Value: Supports ASIL-B relevant logging functions with deterministic write latency (<5 ms) and hardware write lock during CAN message bursts.

Use Scenario: Securing unique device identifiers (UID), TLS root certificates, and OTA update signatures in LPWAN gateways.

IC Role / Device Role / Timing Role: Tamper-resistant nonvolatile storage for cryptographic material; accessed only during secure boot and firmware validation.

Use Value: Prevents unauthorized cloning via hardware-based write protection (WC pin tied high in production) and 200-year data integrity.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AT24C04D-SSHM-T (Microchip)	Same 4-Kbit capacity, 1.7–5.5 V supply, but lacks WC pin; write protection implemented via software address locking.	Requires firmware-level protection logic; unsuitable where hardware-level fail-safe write disable is mandated (e.g., ISO 26262 ASIL-B).	Select if cost-sensitive designs accept software-managed protection and do not require WC pin-level security.
BR24G04FJ-WE2 (ROHM)	1.6–5.5 V operation, 1 MHz I²C support, and built-in error correction code (ECC); package limited to SOP8 and TSSOP8.	Enables faster configuration loading and improved bit-error resilience in noisy industrial environments; ECC adds ~2% area overhead.	Select when system-level reliability requires ECC and higher-speed I²C transfers are available in the host controller.

Compared with AT24C04D-SSHM-T and BR24G04FJ-WE2, the M24C04-RMN6TP provides deterministic hardware write disable via WC pin and broader industrial temperature qualification (−40 °C to +85 °C), making it preferred for safety-critical or high-reliability deployments where software-based protection is insufficient.

Availability

M24C04-RMN6TP is available at Aetrix Electronics and suitable for industrial sensor calibration, embedded system configuration, and automotive body control applications requiring stable component supply across extended product lifecycles.

Supply support for M24C04-RMN6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and memory solutions for industrial, automotive, and consumer markets.

The M24C04 series belongs to ST's serial EEPROM product line, engineered specifically for robust, low-power, I²C-based nonvolatile storage in space-constrained embedded systems with stringent reliability requirements.

FAQ

What is the function of the WC pin on M24C04-RMN6TP?

The WC (Write Control) pin is an active-high hardware write protect input. When driven high, it disables all write operations to the entire 512-byte memory array - including byte and page writes - regardless of I²C command. This prevents accidental overwrites during power transitions or firmware errors. When low or floating, writes are enabled and follow standard I²C protocol timing.

Does M24C04-RMN6TP support I²C clock stretching?

No, the M24C04-RMN6TP does not support clock stretching. It is a simple I²C slave with fixed internal timing: after receiving a stop condition following a write command, it initiates an internal write cycle (t_W ≤ 5 ms) during which it ignores all bus activity. Host systems must poll the ACK bit or wait the maximum t_W before issuing subsequent commands.

Can M24C04-RMN6TP be used with 1.8 V I/O microcontrollers without level shifting?

Yes. The M24C04-RMN6TP supports 1.8 V to 5.5 V supply voltage and has input thresholds defined as 0.2V_CC (low) and 0.8V_CC (high), making it fully compatible with 1.8 V logic levels. Its SDA/SCL inputs operate correctly with 1.8 V microcontrollers (e.g., STM32L0x, nRF528xx) without external level shifters, provided V_CC is set to 1.8 V.

How is device addressing configured for M24C04-RMN6TP in TSSOP8 package?

In the TSSOP8 package, E1 and E2 pins configure bits b3 and b2 of the 7-bit I²C device address (1010 E2 E1 A8 RW). For example, tying E2=VSS and E1=VCC yields address 0xA4 (write) / 0xA5 (read). These pins must be statically pulled to VSS or VCC - floating defaults to 00 - and cannot be dynamically controlled during operation.

M24C04-RMN6TP Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Series:: -

Package/Case:: 8-SOIC (0.154", 3.90mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Verified

Memory Type:: Non-Volatile

Memory Format:: EEPROM

Technology:: EEPROM

Memory Size:: 4Kbit

Memory Organization:: 512 x 8

Memory Interface:: I2C

Clock Frequency:: 400 kHz

Write Cycle Time - Word, Page:: 5ms

Access Time:: 900 ns

Voltage - Supply:: 1.8V ~ 5.5V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 8-SOIC

M24C04-RMN6TP FAQ

1.How can I place an order for M24C04-RMN6TP through Aetrix?

Please submit a Request for Quotation (RFQ) for M24C04-RMN6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for M24C04-RMN6TP reliable?

The price and inventory of M24C04-RMN6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M24C04-RMN6TP is usually 5 days.

3.What payment methods are accepted for M24C04-RMN6TP?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M24C04-RMN6TP transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for M24C04-RMN6TP?

M24C04-RMN6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your M24C04-RMN6TP order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for M24C04-RMN6TP?

For technical support, including M24C04-RMN6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M24C04-RMN6TP requirements.

6.How does Aetrix verify that M24C04-RMN6TP is sourced from the original manufacturer or authorized distributors?

All M24C04-RMN6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M24C04-RMN6TP meets industry standards.

7.What is the process for return or replacement of M24C04-RMN6TP?

All M24C04-RMN6TP units undergo pre-shipment inspection (PSI). If there is an issue with M24C04-RMN6TP, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The M24C04-RMN6TP part is unused and in its original packaging.

Return procedure for M24C04-RMN6TP:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…